Abstract: In an example, an apparatus includes a memory controller. The memory controller may be configured to communicate a request to a computer program for a resource, to initialize a memory, and to perform operations on the memory as instructed. The computer program may be configured to make resources available in response to requests for the resources. The memory controller may be further configured to use the resource in response to an indication from the computer program that the resource is available.

Abstract: Methods of requesting memory spaces and resources using a memory controller are provided. A particular method may include communicating, by a memory controller, a request to a computer program for a resource, and using the resource in response to an indication from the computer program that the resource is available. Another particular method may include communicating a request to a memory controller for at least one of a memory space of a memory or a second resource. The memory controller may be configured to communicate the request from the first resource to a computer program. Another particular method may also include using, by the first resource, at least one of the memory space or the second resource in response to an indication that the memory space or the second resource is available.

Abstract: A method, computer-readable storage media, and a system are provided for managing a scrub. The method may include detecting a trigger for the scrub. The trigger may be based upon a metric of a memory unit. The method may further include scrubbing the memory unit based upon the detection of the trigger.

Abstract: A computer determines a threshold signal voltage of a semiconductor device. The computer determines a first expected signal propagation time for a signal travelling through a first test path of the semiconductor device. The computer transmits a first signal through the first test path. The computer measures a signal voltage and signal propagation time of the first signal. The computer determines that the signal voltage of the first signal does not reach or exceed the threshold signal voltage within the first expected signal propagation time. The computer determines that the first test path contains a defect.

Abstract: A system and method are provided for sharing capacitance. The system may include a first electronic entity with a capacitor having capacitance. The system may further include a switched path in the first electronic entity. The switched path may have a first switched position in which the switched path provides the capacitance to a voltage using device in first electronic entity. The switched path may also have a second switched position in which the switched path provides the capacitance to a second electronic entity. The switched path may also have a third switched position in which the switched path provides the capacitance to both the voltage-using device in the first electronic entity and the second electronic entity.

Abstract: A method, system and computer program product implement memory performance management and enhanced memory reliability of a computer system accounting for system thermal conditions. When a primary memory temperature reaches an initial temperature threshold, reads are suspended to the primary memory and reads are provided to a mirrored memory in a mirrored memory pair, and writes are provided to both the primary memory and the mirrored memory. If the primary memory temperature reaches a second temperature threshold, write operations to the primary memory are also stopped and the primary memory is turned off with DRAM power saving modes such as self timed refresh (STR), and the reads and writes are limited to the mirrored memory in the mirrored memory pair. When the primary memory temperature decreases to below the initial temperature threshold, coherency is recovered by writing a coherent copy from the mirrored memory to the primary memory.

Abstract: In an example, an apparatus includes a memory controller. The memory controller may be configured to communicate a request to a computer program for a resource, to initialize a memory, and to perform operations on the memory as instructed. The computer program may be configured to make resources available in response to requests for the resources. The memory controller may be further configured to use the resource in response to an indication from the computer program that the resource is available.

Abstract: Methods and data processing systems for using a buffer to replace failed memory cells in a memory component are provided. Embodiments include determining that a first copy of data stored within a plurality of memory cells of a memory component contains one or more errors; in response to determining that the first copy contains one or more errors, determining whether a backup cache within the buffer contains a second copy of the data; and in response to determining that the backup cache contains the second copy of the data, transferring the second copy from the backup cache to a location within an error data queue (EDQ) within the buffer and updating the buffer controller to use the location within the EDQ instead of the plurality of memory cells within the memory component.

Abstract: A method for testing and correcting a memory system is described. The method includes selecting a target memory unit of the memory system having a timing margin in response to a trigger to start a timing margin measurement. The stored data in the target memory unit is moved to a spare memory unit. The memory system performs reads and writes of user data from the spare memory unit while measuring the target memory unit. The timing margins of the target memory unit are measured. The reliability of the measured timing margins of the target memory unit based on a timing margin profile is determined.

Abstract: Systems and methods are provided to process a request for a memory space from a memory controller. A particular method may include communicating, by a memory controller, a request for a memory space of a memory to a computer program. The memory controller is configured to initialize the memory, and the memory controller is configured to perform operations on the memory as instructed. The computer program is configured to make memory spaces of the memory available in response to requests for the memory spaces of the memory. The method may also include using, by the memory controller, the memory space in response to an indication from the computer program that the memory space is available. Also provided are systems and methods for copying a memory space by a memory controller to a memory space under exclusive control of the memory controller.

Abstract: An apparatus and method is provided for coupling additional memory to a plurality of processors. The method may include determining the memory requirements of the plurality of processors in a system, comparing the memory requirements of the plurality of processors to an available memory assigned to each of the plurality of processors, and selecting a processor from the plurality of processors that requires additional memory capacity. The apparatus may include a plurality of processors, where the plurality of processors is coupled to a logic element. In addition, the apparatus may include an additional memory coupled to the logic element, where the logic element is adapted to select a processor from the plurality of processors to couple with the additional memory.

Abstract: An apparatus and method is provided for coupling additional memory to a plurality of processors. The method may include determining the memory requirements of the plurality of processors in a system, comparing the memory requirements of the plurality of processors to an available memory assigned to each of the plurality of processors, and selecting a processor from the plurality of processors that requires additional memory capacity. The apparatus may include a plurality of processors, where the plurality of processors is coupled to a logic element. In addition, the apparatus may include an additional memory coupled to the logic element, where the logic element is adapted to select a processor from the plurality of processors to couple with the additional memory.

Abstract: According to one embodiment, a method for error correction in a memory module having ranks is provided where each rank has memory devices. The method includes determining a first mark condition for a first rank of the memory module, the first mark condition based on one or more uncorrectable error occurring in a first memory device in the first rank, placing a first mark in the first memory device, determining a second mark condition for the first rank, the second mark condition based on one or more uncorrectable error occurring in a second memory device in the first rank, placing a second mark in a third memory device in a second rank of the memory module and configuring the first memory device to respond to commands directed to the second rank, wherein configuring the first memory device is based on placing of the first mark and the second mark.

Abstract: A method includes reading, at a memory controller, data from a first dynamic random-access memory (DRAM) die layer of a DRAM stack. The method also includes writing the data to a second DRAM die layer of the DRAM stack. The method further includes sending a request to a test engine to test the first DRAM die layer after writing the data to the second DRAM die layer.

Abstract: Methods of requesting memory spaces and resources using a memory controller are provided. A particular method may include communicating, by a memory controller, a request to a computer program for a resource, and using the resource in response to an indication from the computer program that the resource is available. Another particular method may include communicating a request to a memory controller for at least one of a memory space of a memory or a second resource. The memory controller may be configured to communicate the request from the first resource to a computer program. Another particular method may also include using, by the first resource, at least one of the memory space or the second resource in response to an indication that the memory space or the second resource is available.

Abstract: A method, computer-readable storage media, and a system are provided for managing a scrub. The method may include detecting a trigger for the scrub. The trigger may be based upon a metric of a memory unit. The method may further include scrubbing the memory unit based upon the detection of the trigger.

Abstract: A system and method are provided for sharing capacitance. The system may include a first electronic entity with a capacitor having capacitance. The system may further include a switched path in the first electronic entity. The switched path may have a first switched position in which the switched path provides the capacitance to a voltage using device in first electronic entity. The switched path may also have a second switched position in which the switched path provides the capacitance to a second electronic entity. The switched path may also have a third switched position in which the switched path provides the capacitance to both the voltage-using device in the first electronic entity and the second electronic entity.

Abstract: A method includes directing an access of a memory location of a memory device to an error correction code (ECC) decoder in response to receiving a test activation request indicating the memory location. The method also includes writing a test pattern to the memory location and reading a value from the memory location. The method further includes determining whether a fault is detected at the memory location based on a comparison of the test pattern and the value.

Abstract: According to one embodiment, a method for error correction in a memory module having ranks is provided where each rank has memory devices. The method includes determining a first mark condition for a first rank of the memory module, the first mark condition based on one or more uncorrectable error occurring in a first memory device in the first rank, placing a first mark in the first memory device, determining a second mark condition for the first rank, the second mark condition based on one or more uncorrectable error occurring in a second memory device in the first rank, placing a second mark in a third memory device in a second rank of the memory module and configuring the first memory device to respond to commands directed to the second rank, wherein configuring the first memory device is based on placing of the first mark and the second mark.

Abstract: A method includes reading, at a memory controller, data from a first dynamic random-access memory (DRAM) die layer of a DRAM stack. The method also includes writing the data to a second DRAM die layer of the DRAM stack. The method further includes sending a request to a test engine to test the first DRAM die layer after writing the data to the second DRAM die layer.