Patents by Inventor Diyanesh Babu C. Vidyapoornachary
Diyanesh Babu C. Vidyapoornachary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10453503Abstract: A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.Type: GrantFiled: April 24, 2015Date of Patent: October 22, 2019Assignee: International Business Machines CorporationInventors: Charles A. Kilmer, Anil B. Lingambudi, Warren E. Maule, Diyanesh Babu C. Vidyapoornachary
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Patent number: 9489276Abstract: A method, system and computer program product are provided for implementing enhanced wear leveling in a stack of flash memory chips. A flash memory includes plurality of flash memory chips including a number N data chips and one or more spare chips. To even wear among the plurality of flash memory chips, a memory controller for the flash memory periodically transfers data from a data chip to a current spare chip, the current spare chip becomes a data chip and the selected data chip becomes the current spare chip. Over time, each chip in the stack becomes the spare chip. If a chip becomes nonfunctional, whatever chip is currently the spare chip becomes a permanent data chip and no more rotating is done.Type: GrantFiled: February 20, 2015Date of Patent: November 8, 2016Assignee: International Business Machines CorporationInventors: Gary A. Tressler, Diyanesh Babu C. Vidyapoornachary
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Patent number: 9471451Abstract: A method, system and computer program product are provided for implementing enhanced wear leveling in a stack of flash memory chips. A flash memory includes plurality of flash memory chips including a number N data chips and one or more spare chips. To even wear among the plurality of flash memory chips, a memory controller for the flash memory periodically transfers data from a data chip to a current spare chip, the current spare chip becomes a data chip and the selected data chip becomes the current spare chip. Over time, each chip in the stack becomes the spare chip. If a chip becomes nonfunctional, whatever chip is currently the spare chip becomes a permanent data chip and no more rotating is done.Type: GrantFiled: June 18, 2014Date of Patent: October 18, 2016Assignee: International Business Machines CorporationInventors: Gary A. Tressler, Diyanesh Babu C. Vidyapoornachary
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Patent number: 9411519Abstract: A method and apparatus for implementing performance in a flash memory system in a computer system. A flash memory chip includes a function engine performing garbage collection and scrub operations using an internal bus for data movement. The system includes an on-flash chip memory buffer buffering garbage collection and scrub requests. Garbage collection and scrub operations are interleaved with mainline reads and writes.Type: GrantFiled: April 24, 2015Date of Patent: August 9, 2016Assignee: International Business Machines CorporationInventors: Gary A. Tressler, Diyanesh Babu C. Vidyapoornachary
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Patent number: 9400603Abstract: A method and apparatus for implementing enhanced performance in a flash memory system in a computer system. A flash memory chip includes a function engine performing garbage collection and scrub operations using an internal bus for data movement. The system includes an on-flash chip memory buffer buffering garbage collection and scrub requests. Garbage collection and scrub operations are interleaved with mainline reads and writes.Type: GrantFiled: December 16, 2014Date of Patent: July 26, 2016Assignee: International Business Machines CorporationInventors: Gary A. Tressler, Diyanesh Babu C. Vidyapoornachary
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Patent number: 9389956Abstract: A method, system and memory controller are provided for implementing ECC (Error Correction Codes) control to provide enhanced endurance and data retention of flash memories. The memory controller includes a VT (threshold voltage) monitor to determine VT degradation of cells and blocks; the VT monitor configured to store information about the determined VT degradation; a first ECC engine having a first level of ECC capability; a second ECC engine having a second level of ECC capability, the second level higher than the first level, the second ECC engine having a longer latency than the first ECC engine; a logic to issue a read request to a particular cell/block, and, using the determined VT degradation, use the first ECC engine if the determined VT degradation is less than a threshold and to use the second ECC engine if the determined VT degradation is above the threshold.Type: GrantFiled: January 10, 2014Date of Patent: July 12, 2016Assignee: International Business Machines CorporationInventors: Gary A. Tressler, Diyanesh Babu C. Vidyapoornachary
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Publication number: 20160180900Abstract: A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.Type: ApplicationFiled: April 24, 2015Publication date: June 23, 2016Inventors: Charles A. Kilmer, Anil B. Lingambudi, Warren E. Maule, Diyanesh Babu C. Vidyapoornachary
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Publication number: 20160170656Abstract: A method and apparatus for implementing enhanced performance in a flash memory system in a computer system. A flash memory chip includes a function engine performing garbage collection and scrub operations using an internal bus for data movement, preserving I/O bandwidth. The system includes an on-flash chip memory buffer buffering garbage collection and scrub requests. Garbage collection and scrub operations are interleaved with mainline reads and writes.Type: ApplicationFiled: April 24, 2015Publication date: June 16, 2016Inventors: Gary A. Tressler, Diyanesh Babu C. Vidyapoornachary
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Publication number: 20160170646Abstract: A method and apparatus for implementing enhanced performance in a flash memory system in a computer system. A flash memory chip includes a function engine performing garbage collection and scrub operations using an internal bus for data movement, preserving I/O bandwidth. The system includes an on-flash chip memory buffer buffering garbage collection and scrub requests. Garbage collection and scrub operations are interleaved with mainline reads and writes.Type: ApplicationFiled: December 16, 2014Publication date: June 16, 2016Inventors: Gary A. Tressler, Diyanesh Babu C. Vidyapoornachary
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Patent number: 9342700Abstract: A method, system and memory controller for implementing enhanced security in a memory subsystem including DRAM in a computer system. A memory includes a register to hold scrambling information transmitted from a memory controller; and scrambling circuitry on the memory to scramble at least one of bank select bits and data bits responsive to the scrambling information in the register.Type: GrantFiled: June 16, 2014Date of Patent: May 17, 2016Assignee: International Business Machines CorporationInventors: Timothy J. Dell, Prasanna Jayaraman, Girisankar Paulraj, Diyanesh Babu C. Vidyapoornachary
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Patent number: 9336401Abstract: A method, system and memory controller for implementing enhanced security in a memory subsystem including DRAM in a computer system. A memory includes a register to hold scrambling information transmitted from a memory controller; and scrambling circuitry on the memory to scramble at least one of bank select bits and data bits responsive to the scrambling information in the register.Type: GrantFiled: January 20, 2014Date of Patent: May 10, 2016Assignee: International Business Machines CorporationInventors: Timothy J. Dell, Prasanna Jayaraman, Girisankar Paulraj, Diyanesh Babu C. Vidyapoornachary
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Patent number: 9304856Abstract: A method, system and memory controller are provided for implementing ECC (Error Correction Codes) control to provide enhanced endurance and data retention of flash memories. The memory controller includes a VT (threshold voltage) monitor to determine VT degradation of cells and blocks; the VT monitor configured to store information about the determined VT degradation; a first ECC engine having a first level of ECC capability; a second ECC engine having a second level of ECC capability, the second level higher than the first level, the second ECC engine having a longer latency than the first ECC engine; a logic to issue a read request to a particular cell/block, and, using the determined VT degradation, use the first ECC engine if the determined VT degradation is less than a threshold and to use the second ECC engine if the determined VT degradation is above the threshold.Type: GrantFiled: June 16, 2014Date of Patent: April 5, 2016Assignee: International Business Machines CorporationInventors: Gary A. Tressler, Diyanesh Babu C. Vidyapoornachary
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Publication number: 20150370669Abstract: A method, system and computer program product are provided for implementing enhanced wear leveling in a stack of flash memory chips. A flash memory includes plurality of flash memory chips including a number N data chips and one or more spare chips. To even wear among the plurality of flash memory chips, a memory controller for the flash memory periodically transfers data from a data chip to a current spare chip, the current spare chip becomes a data chip and the selected data chip becomes the current spare chip. Over time, each chip in the stack becomes the spare chip. If a chip becomes nonfunctional, whatever chip is currently the spare chip becomes a permanent data chip and no more rotating is done.Type: ApplicationFiled: February 20, 2015Publication date: December 24, 2015Inventors: Gary A. Tressler, Diyanesh Babu C. Vidyapoornachary
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Publication number: 20150370635Abstract: A method, system and computer program product are provided for implementing enhanced wear leveling in a stack of flash memory chips. A flash memory includes plurality of flash memory chips including a number N data chips and one or more spare chips. To even wear among the plurality of flash memory chips, a memory controller for the flash memory periodically transfers data from a data chip to a current spare chip, the current spare chip becomes a data chip and the selected data chip becomes the current spare chip. Over time, each chip in the stack becomes the spare chip. If a chip becomes nonfunctional, whatever chip is currently the spare chip becomes a permanent data chip and no more rotating is done.Type: ApplicationFiled: June 18, 2014Publication date: December 24, 2015Inventors: Gary A. Tressler, Diyanesh Babu C. Vidyapoornachary
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Publication number: 20150205730Abstract: A method, system and memory controller for implementing enhanced security in a memory subsystem including DRAM in a computer system. A memory includes a register to hold scrambling information transmitted from a memory controller; and scrambling circuitry on the memory to scramble at least one of bank select bits and data bits responsive to the scrambling information in the register.Type: ApplicationFiled: January 20, 2014Publication date: July 23, 2015Applicant: International Business Machines CorporationInventors: Timothy J. Dell, Prasanna Jayaraman, Girisankar Paulraj, Diyanesh Babu C. Vidyapoornachary
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Publication number: 20150205731Abstract: A method, system and memory controller for implementing enhanced security in a memory subsystem including DRAM in a computer system. A memory includes a register to hold scrambling information transmitted from a memory controller; and scrambling circuitry on the memory to scramble at least one of bank select bits and data bits responsive to the scrambling information in the register.Type: ApplicationFiled: June 16, 2014Publication date: July 23, 2015Inventors: Timothy J. Dell, Prasanna Jayaraman, Girisankar Paulraj, Diyanesh Babu C. Vidyapoornachary
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Patent number: 9087168Abstract: According to a method herein, a portion of an electronic circuit is identified. The electronic circuit comprises logic circuitry. The portion of the electronic circuit is designed in at least two versions. Each of the at least two versions is evaluated using a plurality of operating conditions. The current operating conditions are determined. One version of the at least two versions is identified as a selected version based on the performance under the current operating conditions. The selected version has relatively optimal performance based on at least one of clock frequency, supply voltage, and power limit. The selected version is activated for use in the portion of the electronic circuit. The remaining versions of the at least two versions are deactivated.Type: GrantFiled: June 19, 2013Date of Patent: July 21, 2015Assignee: International Business Machines CorporationInventors: John M. Cohn, David J. Hathaway, Sridhar H. Rangarajan, Diyanesh Babu C. Vidyapoornachary
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Publication number: 20150199232Abstract: A method, system and memory controller are provided for implementing ECC (Error Correction Codes) control to provide enhanced endurance and data retention of flash memories. The memory controller includes a VT (threshold voltage) monitor to determine VT degradation of cells and blocks; the VT monitor configured to store information about the determined VT degradation; a first ECC engine having a first level of ECC capability; a second ECC engine having a second level of ECC capability, the second level higher than the first level, the second ECC engine having a longer latency than the first ECC engine; a logic to issue a read request to a particular cell/block, and, using the determined VT degradation, use the first ECC engine if the determined VT degradation is less than a threshold and to use the second ECC engine if the determined VT degradation is above the threshold.Type: ApplicationFiled: June 16, 2014Publication date: July 16, 2015Inventors: Gary A. Tressler, Diyanesh Babu C. Vidyapoornachary
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Publication number: 20150199231Abstract: A method, system and memory controller are provided for implementing ECC (Error Correction Codes) control to provide enhanced endurance and data retention of flash memories. The memory controller includes a VT (threshold voltage) monitor to determine VT degradation of cells and blocks; the VT monitor configured to store information about the determined VT degradation; a first ECC engine having a first level of ECC capability; a second ECC engine having a second level of ECC capability, the second level higher than the first level, the second ECC engine having a longer latency than the first ECC engine; a logic to issue a read request to a particular cell/block, and, using the determined VT degradation, use the first ECC engine if the determined VT degradation is less than a threshold and to use the second ECC engine if the determined VT degradation is above the threshold.Type: ApplicationFiled: January 10, 2014Publication date: July 16, 2015Applicant: International Business Machines CorporationInventors: Gary A. Tressler, Diyanesh Babu C. Vidyapoornachary
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Publication number: 20140375380Abstract: According to a method herein, a portion of an electronic circuit is identified. The electronic circuit comprises logic circuitry. The portion of the electronic circuit is designed in at least two versions. Each of the at least two versions is evaluated using a plurality of operating conditions. The current operating conditions are determined. One version of the at least two versions is identified as a selected version based on the performance under the current operating conditions. The selected version has relatively optimal performance based on at least one of clock frequency, supply voltage, and power limit. The selected version is activated for use in the portion of the electronic circuit. The remaining versions of the at least two versions are deactivated.Type: ApplicationFiled: June 19, 2013Publication date: December 25, 2014Inventors: John M. Cohn, David J. Hathaway, Sridhar H. Rangarajan, Diyanesh Babu C. Vidyapoornachary