Patents by Inventor Diyanesh Babu Chinnakkonda Vidyapoornachary
Diyanesh Babu Chinnakkonda Vidyapoornachary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111598Abstract: In an embodiment, a processor may include a plurality of processing engines and a sequencing circuit. The sequencing circuit may be to: detect a completed execution of a first workload by a first processing engine; in response to a detection of the completed execution of the first workload by the first processing engine, identify at least one processing engine specified as consecutive to the first processing engine in a sequence mapping; and activate the at least one processing engine specified as consecutive to execute a second workload.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Inventors: Shidlingeshwar Khatakalle, Vijay Anand Mathiyalagan, Diyanesh Babu Chinnakkonda Vidyapoornachary
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Publication number: 20230137769Abstract: Systems, apparatuses and methods may provide for operating system (OS) technology that determines an average bandwidth consumption with respect to a memory device, wherein the average bandwidth consumption is dedicated to a previous execution of a thread in a multi-threaded execution environment, stores the average bandwidth consumption, and sends the average bandwidth consumption to a power management unit in response to a subsequent execution of the thread being scheduled. Additionally, logic hardware technology may include a first set of registers to accumulate an average bandwidth consumption for a plurality of threads on a per thread basis with respect to the memory device, wherein the average bandwidth consumption corresponds to previous executions of the plurality of threads. The logic hardware technology determines a minimum bandwidth demand based on the average bandwidth consumption and sets a dynamic voltage and frequency scaling point based on the minimum bandwidth demand.Type: ApplicationFiled: November 3, 2021Publication date: May 4, 2023Inventors: Vijay Anand Mathiyalagan, Stephen H. Gunther, Shidlingeshwar Khatakalle, Diyanesh Babu Chinnakkonda Vidyapoornachary
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Publication number: 20220188019Abstract: A memory system includes a first set of memory devices, a second set of memory devices, and a memory controller circuit system. The memory controller circuit system groups a first one of the memory devices in each of the first and the second sets into a first virtual memory rank based on eye margins of first data signals sampled by the first virtual memory rank. The memory controller circuit system groups a second one of the memory devices in each of the first and the second sets into a second virtual memory rank based on eye margins of second data signals sampled by the second virtual memory rank. The memory controller circuit system accesses the memory devices in the first virtual memory rank separately from the memory devices in the second virtual memory rank during data access operations.Type: ApplicationFiled: March 7, 2022Publication date: June 16, 2022Applicant: Intel CorporationInventors: Ramkumar Jayaraman, Saravanan Sethuraman, Diyanesh Babu Chinnakkonda Vidyapoornachary, Krishnaprasad H
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Patent number: 10545824Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.Type: GrantFiled: November 10, 2017Date of Patent: January 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diyanesh Babu Chinnakkonda Vidyapoornachary, Timothy J. Dell, Marc A. Gollub, Anil B. Lingambudi
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Publication number: 20180067803Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.Type: ApplicationFiled: November 10, 2017Publication date: March 8, 2018Inventors: Diyanesh Babu Chinnakkonda Vidyapoornachary, Timothy J. Dell, Marc A. Gollub, Anil B. Lingambudi
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Patent number: 9858145Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.Type: GrantFiled: August 26, 2015Date of Patent: January 2, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diyanesh Babu Chinnakkonda Vidyapoornachary, Timothy J. Dell, Marc A. Gollub, Anil B. Lingambudi
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Patent number: 9703630Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.Type: GrantFiled: June 8, 2015Date of Patent: July 11, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diyanesh Babu Chinnakkonda Vidyapoornachary, Timothy J. Dell, Marc A. Gollub, Anil B. Lingambudi
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Publication number: 20160357628Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.Type: ApplicationFiled: June 8, 2015Publication date: December 8, 2016Inventors: Diyanesh Babu Chinnakkonda Vidyapoornachary, Timothy J. Dell, Marc A. Gollub, Anil B. Lingambudi
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Publication number: 20160357629Abstract: A system and method of performing selective error coding in memory management of a memory device are described. The method includes performing a process of detecting and correcting memory errors in the memory of the memory device either prior to or after a chip mark associated with the memory device is in place. The method also includes localizing hard errors of the memory device based on a second process of detecting the memory errors in the memory of the memory device, the hard errors being persistent memory errors that persist from the process of detecting and correcting the memory errors to the second process, determining an extent of the hard errors based on the localizing, and preventing placement of the chip mark or removing the chip mark after de-allocating one or more ranges of addresses based on a result of the determining the extent of the hard errors.Type: ApplicationFiled: August 26, 2015Publication date: December 8, 2016Inventors: Diyanesh Babu Chinnakkonda Vidyapoornachary, Timothy J. Dell, Marc A. Gollub, Anil B. Lingambudi
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Patent number: 9252131Abstract: By arranging dies in a stack such that failed cores are aligned with adjacent good cores, fast connections between good cores and cache of failed cores can be implemented. Cache can be allocated according to a priority assigned to each good core, by latency between a requesting core and available cache, and/or by load on a core.Type: GrantFiled: October 10, 2013Date of Patent: February 2, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Edgar R. Cordero, Anand Haridass, Subrat K. Panda, Saravanan Sethuraman, Diyanesh Babu Chinnakkonda Vidyapoornachary
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Publication number: 20150106569Abstract: By arranging dies in a stack such that failed cores are aligned with adjacent good cores, fast connections between good cores and cache of failed cores can be implemented. Cache can be allocated according to a priority assigned to each good core, by latency between a requesting core and available cache, and/or by load on a core.Type: ApplicationFiled: October 10, 2013Publication date: April 16, 2015Applicant: International Business Machines CorporationInventors: Edgar R. Cordero, Anand Haridass, Subrat K. Panda, Saravanan Sethuraman, Diyanesh Babu Chinnakkonda Vidyapoornachary