Patents by Inventor Dmitri A. Choutov

Dmitri A. Choutov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11664427
    Abstract: A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench. The superlattice layer may comprise stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer. Each at least one non-semiconductor monolayer of each group of layers may be constrained within a crystal lattice of adjacent base semiconductor portions. The vertical semiconductor device may also include a doped semiconductor layer adjacent the superlattice layer, and a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.
    Type: Grant
    Filed: May 23, 2022
    Date of Patent: May 30, 2023
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
  • Publication number: 20220285498
    Abstract: A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice layer extending vertically adjacent the at least one trench. The superlattice layer may comprise stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer. Each at least one non-semiconductor monolayer of each group of layers may be constrained within a crystal lattice of adjacent base semiconductor portions. The vertical semiconductor device may also include a doped semiconductor layer adjacent the superlattice layer, and a conductive body adjacent the doped semiconductor layer on a side thereof opposite the superlattice layer and defining a vertical semiconductor device contact.
    Type: Application
    Filed: May 23, 2022
    Publication date: September 8, 2022
    Inventors: ROBERT JOHN STEPHENSON, RICHARD BURTON, DMITRI CHOUTOV, NYLES WYNN CODY, DANIEL CONNELLY, ROBERT J. MEARS, ERWIN TRAUTMANN
  • Patent number: 11387325
    Abstract: A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner. The superlattice liner may include a plurality of stacked groups of layers, each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group being constrained within a crystal lattice of adjacent base semiconductor portions. The device may also include a semiconductor layer on the superlattice liner and including a dopant constrained therein by the superlattice liner, and a conductive body within the at least one trench defining a source contact.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: July 12, 2022
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
  • Patent number: 11075078
    Abstract: A method for making a semiconductor device may include forming an isolation region adjacent an active region in a semiconductor substrate, and selectively etching the active region so that an upper surface of the active region is below an adjacent surface of the isolation region and defining a stepped edge therewith. The method may further include forming a superlattice overlying the active region. The superlattice may include stacked groups of layers, with each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: July 27, 2021
    Assignee: ATOMERA INCORPORATED
    Inventors: Nyles Wynn Cody, Keith Doran Weeks, Robert John Stephenson, Richard Burton, Yi-Ann Chen, Dmitri Choutov, Hideki Takeuchi, Yung-Hsuan Yang
  • Publication number: 20210074814
    Abstract: A vertical semiconductor device may include a semiconductor substrate having at least one trench therein, and a superlattice liner at least partially covering sidewall portions of the at least one trench and defining a gap between opposing sidewall portions of the superlattice liner. The superlattice liner may include a plurality of stacked groups of layers, each group of layers comprising stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer, with each at least one non-semiconductor monolayer of each group being constrained within a crystal lattice of adjacent base semiconductor portions. The device may also include a semiconductor layer on the superlattice liner and including a dopant constrained therein by the superlattice liner, and a conductive body within the at least one trench defining a source contact.
    Type: Application
    Filed: November 23, 2020
    Publication date: March 11, 2021
    Inventors: ROBERT JOHN STEPHENSON, RICHARD BURTON, DMITRI CHOUTOV, NYLES WYNN CODY, DANIEL CONNELLY, ROBERT J. MEARS, ERWIN TRAUTMANN
  • Patent number: 10879356
    Abstract: A method for making a semiconductor device may include forming a trench in a semiconductor substrate, and forming a superlattice liner covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and forming a conductive body within the trench.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: December 29, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
  • Patent number: 10777451
    Abstract: A semiconductor device may include a semiconductor substrate having a trench therein, and a superlattice liner at least partially covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and a conductive body within the trench.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: September 15, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J Mears, Erwin Trautmann
  • Publication number: 20190280090
    Abstract: A semiconductor device may include a semiconductor substrate having a trench therein, and a superlattice liner at least partially covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and a conductive body within the trench.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 12, 2019
    Inventors: ROBERT JOHN STEPHENSON, RICHARD BURTON, DMITRI CHOUTOV, NYLES WYNN CODY, DANIEL CONNELLY, ROBERT J, MEARS, ERWIN TRAUTMANN
  • Publication number: 20190279897
    Abstract: A method for making a semiconductor device may include forming a trench in a semiconductor substrate, and forming a superlattice liner covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and forming a conductive body within the trench.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 12, 2019
    Inventors: Robert John Stephenson, Richard Burton, Dmitri Choutov, Nyles Wynn Cody, Daniel Connelly, Robert J. Mears, Erwin Trautmann
  • Patent number: 8598797
    Abstract: A driver device for driving an LED lighting device includes at least one power switch adapted to operate at a switching frequency of greater than 500 KHz and adapted to control the driving current provided to the LED lighting device. Operating the power switch at such a high frequency allows a substantial reduction in passive devices such as inductors and capacitors.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: December 3, 2013
    Assignee: Luxera, Inc.
    Inventors: Dmitri A. Choutov, Leonard S. Livschitz
  • Patent number: 8587956
    Abstract: A compact driver device for driving an LED lighting device is provided. The driver device includes a substrate, power capacitor that provides LED driving current to drive the LED lighting device, and a power resistor. Advantageously, the power capacitor and the power resistor are attached to the substrate and are solderlessly connected to each other to provide a very compact driver device.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: November 19, 2013
    Assignee: Luxera, Inc.
    Inventors: Dmitri A. Choutov, Leonard S. Livschitz
  • Patent number: 8461775
    Abstract: An integrated 3-dimensional inductor device is provided. The inductor device includes a substrate having an electrical trace and a 3-dimensional inductor attached to the substrate. The inductor includes a magnetic core and a coil whose windings are formed from the electrical traces of the substrate and conductive material in the interconnect vias.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: June 11, 2013
    Assignee: Luxera, Inc.
    Inventors: Dmitri A. Choutov, Leonard S. Livschitz
  • Publication number: 20110285302
    Abstract: A driver device for driving an LED lighting device includes at least one power switch adapted to operate at a switching frequency of greater than 500 KHz and adapted to control the driving current provided to the LED lighting device. Operating the power switch at such a high frequency allows a substantial reduction in passive devices such as inductors and capacitors.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 24, 2011
    Inventors: Dmitri A. Choutov, Leonard S. Livschitz
  • Publication number: 20110285312
    Abstract: An integrated 3-dimensional inductor device is provided. The inductor device includes a substrate having an electrical trace and a 3-dimensional inductor attached to the substrate. The inductor includes a magnetic core and a coil whose windings are formed from the electrical traces of the substrate and conductive material in the interconnect vias.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 24, 2011
    Inventors: Dmitri A. Choutov, Leonard S. Livschitz
  • Publication number: 20110193491
    Abstract: A compact driver device for driving an LED lighting device is provided. The driver device includes a substrate, power capacitor that provides LED driving current to drive the LED lighting device, and a power resistor. Advantageously, the power capacitor and the power resistor are attached to the substrate and are solderlessly connected to each other to provide a very compact driver device.
    Type: Application
    Filed: January 31, 2011
    Publication date: August 11, 2011
    Inventors: Dmitri A. CHOUTOV, Leonard S. LIVSCHITZ
  • Publication number: 20100220215
    Abstract: Embodiments of the present invention are video acquisition and processing systems. One embodiment of the present invention, video acquisition and processing systems include a sensor, image signal processor, and video compression and decompression components fully integrated in a single integrated circuit. The integrated sensor and image signal processor feature highly parallel transmission of image data to the video compression and decompression component. This highly parallel, pipelined, special-purpose integrated-circuit implementation offers cost-effective video acquisition and image data processing and an extremely large computational bandwidth with relatively low power consumption and low-latency for processing video signals.
    Type: Application
    Filed: August 24, 2009
    Publication date: September 2, 2010
    Inventors: Jorge Rubinstein, Albert Rooyakkers, Farooq Habib, Dmitri A. Choutov
  • Patent number: 7431796
    Abstract: An apparatus for low-damage, anisotropic etching of substrates having the substrate mounted upon a mechanical support located within an ac or dc plasma reactor. The mechanical support is independent of the plasma reactor generating apparatus and capable of being electrically biased. The substrate is subjected to a plasma of low-energy electrons and a species reactive with the substrate. An additional structure capable of being electrically biased can be placed within the plasma to control further the extraction or retardation of particles from the plasma.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: October 7, 2008
    Assignee: Georgia Tech Research Corporation
    Inventors: Kevin P. Martin, Harry P. Gillis, Dmitri A. Choutov
  • Patent number: 6852195
    Abstract: An apparatus for low-damage, anisotropic etching of substrates having the substrate mounted upon a mechanical support located within an ac or dc plasma reactor. The mechanical support is independent of the plasma reactor generating apparatus and capable of being electrically biased. The substrate is subjected to plasma of low-energy electrons and a species reactive with the substrate. An additional structure capable of being electrically biased can be placed within the plasma to control further the extraction or retardation of particles from the plasma.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: February 8, 2005
    Assignee: Georgia Tech Research Corporation
    Inventors: Kevin P. Martin, Harry P. Gillis, Dmitri A. Choutov
  • Patent number: 6593200
    Abstract: A method of forming a semiconductor device with an inductor and/or high speed interconnect. The method comprises forming an epitaxial layer over the substrate, forming an opening through the epitaxial layer to expose an underlying region of the substrate, forming a first dielectric material within the opening of the epitaxial layer, planarizing the first dielectric layer, forming a second dielectric material layer over the first dielectric material layer, and then forming a metallized inductor over the second dielectric material layer above the opening of the epitaxial layer. In this case, since the inductor and the high speed interconnect do not overlie the conductive epitaxial layer, the degradation in the Q-factor of the inductor, loss characteristics of the high speed interconnect, and ‘cross-talk’ between conductors are substantially reduced. The resulting semiconductor device is also disclosed.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: July 15, 2003
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Alexander Kalnitsky, Dmitri A. Choutov, Geoffrey C. Stutzin, Robert F. Scheer
  • Publication number: 20030096487
    Abstract: A method of forming a semiconductor device with an inductor and/or high speed interconnect. The method comprises forming an epitaxial layer over the substrate, forming an opening through the epitaxial layer to expose an underlying region of the substrate, forming a first dielectric material within the opening of the epitaxial layer, planarizing the first dielectric layer, forming a second dielectric material layer over the first dielectric material layer, and then forming a metallized inductor over the second dielectric material layer above the opening of the epitaxial layer. In this case, since the inductor and the high speed interconnect do not overlie the conductive epitaxial layer, the degradation in the Q-factor of the inductor, loss characteristics of the high speed interconnect, and ‘cross-talk’ between conductors are substantially reduced. The resulting semiconductor device is also disclosed.
    Type: Application
    Filed: November 20, 2001
    Publication date: May 22, 2003
    Inventors: Alexander Kalnitsky, Dmitri A. Choutov, Geoffrey C. Stutzin, Robert F. Scheer