Abstract: A multilayer circuit (400) includes a base layer (205) which has a number of base vias (247, 415), a first overlying layer (215) formed on the base layer (205) and having a first routing section (210) and a second overlying layer (220) formed on the first overlying layer (215). The second overlying layer (220) has a second routing section (210) and is formed using the same set of masks. The first routing section (210) and the second routing section (210) form a unique electrical pathway (248) between a base via (247) and an element in an overlying layer. A method for forming a multilayer circuit is also provided.

Abstract: A memristive device is disclosed herein. The device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. At least two mobile species are present in the active region. Each of the at least two mobile species is configured to define a separate state variable of the memristive device.

Abstract: A capacitive crossbar array includes a first set of conductors and a second set of conductors which intersect to form crosspoints. A nonlinear capacitive device is interposed between a first conductor within the first set and a second conductor within the second set at a crosspoint. The nonlinear capacitive device is configured to store information which is accessible through said first conductor and said second conductor. A method for utilizing a capacitive crossbar array is also provided.

Abstract: Resistive switches and related methods are provided. Such a resistive switch includes an active material in contact with opposite end electrodes. The active material defines electron traps that capture or release charges in accordance with applied switching voltages. Resistive switches are characterized by ON state and OFF state resistance curves. Resistance ratios of ten times or more are exhibited. The state of a resistive switch is determined using sensing voltages lesser then the switching threshold.

Abstract: A reconfigurable multilayer circuit (400) includes a complimentary metal-oxide-semiconductor (CMOS) layer (210) having control circuitry, logic gates (515), and at least two crossbar arrays (205, 420) which overlie the CMOS layer (210). The at least two crossbar arrays (205, 420) are configured by the control circuitry and form reconfigurable interconnections between the logic gates (515) within the CMOS layer (210).

Abstract: One embodiment of the present invention is directed to hybrid-nanoscale/microscale device comprising a microscale layer that includes microscale and/or submicroscale circuit components and that provides an array of microscale or submicroscale pins across an interface surface; and at least two nanoscale-layer sub-layers within a nanoscale layer that interfaces to the microscale layer, each nanoscale-layer sub-layer containing regularly spaced, parallel nanowires, each nanowire of the at least two nanoscale-layer sub-layers in electrical contact with at most one pin provided by the microscale layer, the parallel nanowires of successive nanoscale-layer sub-layers having different directions, with the nanowires of successive nanoscale-layer sub-layers intersecting to form programmable crosspoints.

Abstract: A three dimensional multilayer circuit includes a via array made up of a set of first vias and a set of second vias and an area distributed CMOS layer configured to selectively address said first vias and said second vias. At least two crossbar arrays overlay the area distributed CMOS layer. These crossbar arrays include a plurality of intersecting crossbar segments and programmable crosspoint devices which are interposed between the intersecting crossbar segments. The vias are connected to the crossbar segments such that each programmable crosspoint devices can be uniquely accessed using a first via and a second via.

Abstract: A controlled switching memristor includes a first electrode, a second electrode, and a switching layer positioned between the first electrode and the second electrode. The switching layer includes a material to switch between an ON state and an OFF state, in which at least one of the first electrode, the second electrode, and the switching layer is to generate a permanent field within the memristor to enable a speed and an energy of switching from the ON state to the OFF state to be substantially symmetric to a speed and energy of switching from the OFF state to the ON state.

Abstract: A test circuit tests a nonvolatile circuit element having multiple intermediate states. The test circuit includes a waveform generator configured to apply a waveform to the circuit element connected to the test circuit. The waveform includes stress pulses applied to the circuit element over time. A detector detects a parameter of the circuit element as the waveform is applied to the circuit element.

Abstract: Resistive switches and related methods are provided. Such a resistive switch includes an active material in contact with opposite end electrodes. The active material defines electron traps that capture or release charges in accordance with applied switching voltages. Resistive switches are characterized by ON state and OFF state resistance curves. Resistance ratios of ten times or more are exhibited. The state of a resistive switch is determined using sensing voltages lesser then the switching threshold.

Abstract: A multilayer circuit (400) includes a base layer (205) which has a number of base vias (247, 415), a first layer (215) formed on the base layer (205) and having a first routing section (210) and a second overlying layer (220) formed on the first overlying layer (215).

Abstract: A capacitive crossbar array (100) includes a first set of conductors (102) and a second set of conductors (104) which intersect to form crosspoints. A nonlinear capacitive device (106) is interposed between a first conductor (103) within the first set (102) and a second conductor (105) within the second set (104) at a crosspoint. The nonlinear capacitive device (106) is configured to store information which is accessible through said first conductor (103) and said second conductor (105). A method for utilizing a capacitive crossbar array (100) is also provided.

Abstract: A reconfigurable multilayer circuit (400) includes a complimentary metal-oxide-semiconductor (CMOS) layer (210) having control circuitry, logic gates (515), and at least two crossbar arrays (205, 420) which overlie the CMOS layer (210). The at least two crossbar arrays (205, 420) are configured by the control circuitry and form reconfigurable interconnections between the logic gates (515) within the CMOS layer (210).

Abstract: One embodiment of the present invention is directed to hybrid-nanoscale/microscale device comprising a microscale layer that includes microscale and/or submicroscale circuit components and that provides an array of microscale or submicroscale pins across an interface surface; and at least two nanoscale-layer sub-layers within a nanoscale layer that interfaces to the microscale layer, each nanoscale-layer sub-layer containing regularly spaced, parallel nanowires, each nanowire of the at least two nanoscale-layer sub-layers in electrical contact with at most one pin provided by the microscale layer, the parallel nanowires of successive nanoscale-layer sub-layers having different directions, with the nanowires of successive nanoscale-layer sub-layers intersecting to form programmable crosspoints.

Abstract: A three dimensional multilayer circuit (400) includes a via array (325, 330) made up of a set of first vias (325) and a set of second vias (330) and an area distributed CMOS layer (310) configured to selectively address said first vias (325) and said second vias (330). At least two crossbar arrays (305, 420) overlay the area distributed CMOS layer (310). These crossbar arrays (305, 420) include a plurality of intersecting crossbar segments (320, 322) and programmable cross-point devices (315) which are interposed between the intersecting crossbar segments (320, 322). The vias (325, 330) are connected to the crossbar segments (320, 322) such that each programmable crosspoint devices (315) can be uniquely accessed using a first via (325) and a second via (330).

Abstract: A switchable junction (600) with an intrinsic diode includes a first electrode (635) and second electrode (640). A first memristive matrix (605) forms an electrical interface (625) with the first electrode (635) which has a programmable conductance. A semiconductor matrix (615) is electrical contact with the first memristive matrix (605) and forms a rectifying diode interface (630) with the second electrode (640).

Abstract: Methods and apparatus pertaining to memory resistors are provided. Electronic circuitry determines energy for changing a non-volatile resistance of a memristor from a present value to a target value. An electric charge corresponding to the energy is stored. An electric pulse is applied to the memristor using the stored charge. The newly adjusted resistance of the memristor is sensed and compared to the target value. Additional electric pulses can be applied in accordance with the comparison. Memristor adjustment by way of feedback control is thus contemplated by the present teachings.

Abstract: A memristive device is disclosed herein. The device includes a first electrode, a second electrode, and an active region disposed between the first and second electrodes. At least two mobile species are present in the active region. Each of the at least two mobile species is configured to define a separate state variable of the memristive device.

Abstract: A test circuit tests a nonvolatile circuit element having multiple intermediate states. The test circuit includes a waveform generator configured to apply a waveform to the circuit element connected to the test circuit. The waveform includes stress pulses applied to the circuit element over time. A detector detects a parameter of the circuit element as the waveform is applied to the circuit element.