Abstract: An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs. Various algorithms for tuning the memory cells to contain the correct weight values are disclosed.

Abstract: A security primitive for an integrated circuit comprises an array of floating-gate transistors monolithically integrated into the integrated circuit and coupled to one another in a crossbar configuration. The floating-gate transistors have instance-specific process-induced variations in analog behavior to provide one or more reconfigurable physically unclonable functions (PUFs).

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

Abstract: There are disclosed memristors and memristor fabrication methods. A memristor may include a stack of four functional elements including, in sequence, a first electrode, a barrier layer, an oxygen-deficient switching layer, and a second electrode.

Abstract: A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

Abstract: An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs.

Abstract: There are disclosed memristors and memristor fabrication methods. A memristor may include a stack of four functional elements including, in sequence, a first electrode, a barrier layer, an oxygen-deficient switching layer, and a second electrode.

Abstract: A nanoscale switching device has an active region containing a switching material capable of carrying a species of dopants and transporting the dopants under an electrical field. The switching device has first, second and third electrodes with nanoscale widths. The active region is disposed between the first and second electrodes. A resistance modifier layer, which has a non-linear voltage-dependent resistance, is disposed between the second and third electrodes.

Abstract: A memristive device includes a first electrode; a second electrode; a junction between the first electrode and the second electrode, the junction including a semiconductor matrix and particles embedded in the semiconductor matrix, the particles being configured to hold a selectable level of electrical charge, the electrical charge controlling the amount of current flowing through the junction for a given reading voltage.

Abstract: A memristive switch device can comprise a switch formed between a first electrode and a second electrode, where the switch includes a memristive layer and a select layer directly adjacent the memristive layer. The select layer blocks current to the memristive layer over a symmetric bipolar range of subthreshold voltages applied between the first and second electrodes.

Abstract: A memcapacitive device includes a first electrode having a first end and a second end and a second electrode. The device has a memcapacitive matrix interposed between the first electrode and the second electrode. The memcapacitive matrix has a non-linear capacitance with respect to a voltage across the first electrode and the second electrode. The memcapacitive matrix is configured to alter a signal applied on the first end by at least one of a) changing at least one of a rise-time and a fall-time of the signal and b) delaying the transmission of the signal based on the application of a programming voltage across the first electrode and the second electrode.

Abstract: A memory element is provided that includes a first electrode, a second electrode, and an active region disposed between the first electrode and the second electrode, wherein at least a portion of the active region comprises an elastically deformable material, and wherein deformation of the elastically deformable material causes said memory element to change from a lower conductive state to a higher conductive state. A multilayer structure also is provided that includes a base and a multilayer circuit disposed above the base, where the multilayer circuit includes at least of the memory elements including the elastically deformable material.

Abstract: A memristive switch device can comprise a switch formed between a first electrode and a second electrode, where the switch includes a memristive layer and a select layer directly adjacent the memristive layer. The select layer blocks current to the memristive layer over a symmetric bipolar range of subthreshold voltages applied between the first and second electrodes.

Abstract: A memristive device (200) includes a first electrode (104); a second electrode (102); a junction (106) between the first electrode (104) and the second electrode (102), the junction (106) including a semiconductor matrix (230) and particles (240) embedded in the semiconductor matrix (230), the particles (240) being configured to hold a selectable level of electrical charge, the electrical charge controlling the amount of current flowing through the junction (106) for a given reading voltage.

Abstract: A nanoscale switching device has an active region containing a switching material capable of carrying a species of dopants and transporting the dopants under an electrical held. The switching device has first, second and third electrodes with nanoscale widths. The active region is disposed between the first and second electrodes. A resistance modifier layer, which has a non-linear voltage-dependent resistance, is disposed between the second and third electrodes.

Abstract: A memcapacitive device includes a first electrode having a first end and a second end and a second electrode. The device has a memcapacitive matrix interposed between the first electrode and the second electrode. The memcapacitive matrix has a non-linear capacitance with respect to a voltage across the first electrode and the second electrode. The memcapacitive matrix is configured to alter a signal applied on the first end by at least one of a) changing at least one of a rise-time and a fall-time of the signal and b) delaying the transmission of the signal based on the application of a programming voltage across the first electrode and the second electrode.