Patents by Inventor Dmitri Yurievich Pavlov

Dmitri Yurievich Pavlov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Unified computation systems and methods for iterative multiplication and division, efficient overflow detection systems and methods for integer division, and tree-based addition systems and methods for single-cycle multiplication
    Patent number: 9804998
    Abstract: A unified computation unit for iterative multiplication and division may include an architecture having a unified integer iterative multiplication and division circuit. A method may include a device receiving a dividend and a divisor for a division operation, separating the dividend into two parts based on the determining, and evaluating whether an overflow situation exists based on the two parts. A single-cycle multiplication unit may include a multi-operand addition schema for partial products compression that implements tree-based addition methods for single-cycle multiplication operations.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: October 31, 2017
    Assignee: Intel Corporation
    Inventors: Alexander Sergeevich Rumyantsev, Dmitri Yurievich Pavlov, Alexander Nikolayevich Redkin, Daniil Valentinovich Demidov, Dmitry Anatolievich Gusev
  • UNIFIED COMPUTATION SYSTEMS AND METHODS FOR ITERATIVE MULTIPLICATION AND DIVISION, EFFICIENT OVERFLOW DETECTION SYSTEMS AND METHODS FOR INTEGER DIVISION, AND TREE-BASED ADDITION SYSTEMS AND METHODS FOR SINGLE-CYCLE MULTIPLICATION
    Publication number: 20140046996
    Abstract: A unified computation unit for iterative multiplication and division may include an architecture having a unified integer iterative multiplication and division circuit. A method may include a device receiving a dividend and a divisor for a division operation, separating the dividend into two parts based on the determining, and evaluating whether an overflow situation exists based on the two parts. A single-cycle multiplication unit may include a multi-operand addition schema for partial products compression that implements tree-based addition methods for single-cycle multiplication operations.
    Type: Application
    Filed: November 29, 2011
    Publication date: February 13, 2014
    Applicant: Intel Corporation
    Inventors: Alexander Sergeevich Rumyantsev, Dmitri Yurievich Pavlov, Alexander Nikolayevich Redkin, Daniil Valentinovich Demidov, Dmitry Anatolievich Gusev
  • Layered decoder and method for performing layered decoding
    Patent number: 8234537
    Abstract: Embodiments of a decoder and method of decoding blocks of soft bits in a wireless receiver are generally described herein. Other embodiments may be described and claimed. In some embodiments, a memory is initialized with encoded input data and updated with sums of extrinsic reliabilities. Decoded output data is provided from the memory after a predetermined number of iterations.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: July 31, 2012
    Assignee: Intel Corporation
    Inventors: Dmitri Yurievich Pavlov, Mikhail Yurievich Lyakh
  • LAYERED DECODER AND METHOD FOR PERFORMING LAYERED DECODING
    Publication number: 20090037791
    Abstract: Embodiments of a decoder and method of decoding blocks of soft bits in a wireless receiver are generally described herein. Other embodiments may be described and claimed. In some embodiments, a memory is initialized with encoded input data and updated with sums of extrinsic reliabilities. Decoded output data is provided from the memory after a predetermined number of iterations.
    Type: Application
    Filed: March 31, 2006
    Publication date: February 5, 2009
    Inventors: Dmitri Yurievich Pavlov, Mikhail Yurievich Lyakh