Patents by Inventor Dmitrity Rumynin

Dmitrity Rumynin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Multiplication logic circuit
    Patent number: 7275076
    Abstract: A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length columns. The output of the maximal length parallel counters are then further reduced by a second level of reduction logic comprising logic circuits with asymmetric delays in order to compensate for the differential delays experienced by the outputs of the maximal length parallel counters.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: September 25, 2007
    Assignee: Arithmatica Limited
    Inventors: Sunil Talwar, Dmitrity Rumynin
  • Multiplication logic circuit
    Publication number: 20040103135
    Abstract: A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length columns. The output of the maximal length parallel counters are then further reduced by a second level of reduction logic comprising logic circuits with asymmetric delays in order to compensate for the differential delays experienced by the outputs of the maximal length parallel counters.
    Type: Application
    Filed: September 22, 2003
    Publication date: May 27, 2004
    Inventors: Sunil Talwar, Dmitrity Rumynin