Abstract: An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.

Abstract: An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.

Abstract: An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.

Abstract: Multi-port power prediction for power management of data storage devices is disclosed. For certain embodiments, a host interface within a port multiplier receives host messages from a host device for a plurality of data storage devices. The port multiplier then uses a plurality of ports to forward device messages to the data storage devices based upon the host messages. A power prediction controller determines target data storage devices for access commands within the host messages and generates power commands to adjust power modes for target data storage devices to place the target data storage devices in active power modes prior to access according to the access commands from the host device. Power up latency is thereby reduced or eliminated for the target data storage devices.

Abstract: Multi-port power prediction for power management of data storage devices is disclosed. For certain embodiments, a host interface within a port multiplier receives host messages from a host device for a plurality of data storage devices. The port multiplier then uses a plurality of ports to forward device messages to the data storage devices based upon the host messages. A power prediction controller determines target data storage devices for access commands within the host messages and generates power commands to adjust power modes for target data storage devices to place the target data storage devices in active power modes prior to access according to the access commands from the host device. Power up latency is thereby reduced or eliminated for the target data storage devices.

Abstract: An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.