Abstract: The invention relates to a method for influencing the selection of a type and form of a circuit implementation in at least one layer in a given integration task for at least one integrated circuit in a wafer composite, a module on a 2-dimensional carrier substrate, or a compact module. In one embodiment, a plurality of electric or electronic components are spatially arranged and to be electrically connected. Completed solutions x are stored in a database, and each of the completed solutions includes properties for the given integration task. The completed solutions define a destination space from which a solution is selectable by operating elements and determines a type and form of circuit implementation as a result of the given integration task, and aggregates the plurality of electric and electronic components in one of a plurality of integration technologies.

Abstract: The invention relates to a method for influencing a selecting a “type and form of a circuit implementation” in at least one layer (L1,L2) in a given integration task for an integrated circuit or many thereof aggregated in a wafer composite, a module on a 2-dimensional carrier substrate, or a compact module. A plurality of electric or electronic components is spatially arranged and electrically conductively to be connected. To this end a plurality of completed solutions x (5;5a,5b) are stored and available in a database (10), and each of the completed solutions includes a set of properties, wherein each set includes at least one of the following properties for the given integration task: a technology for integration, a package or installation size, a number of layers (physical layers) for conductors or line in a vertical direction and a line length or conductor length.