Patents by Inventor Dmitry E. Ryzhov
Dmitry E. Ryzhov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240406380Abstract: A block of a video frame can be encoded using inter-prediction, and the motion vector of the block can be encoded based on a motion vector reference of a merge candidate. Some video codecs allow a large range of temporal and spatial neighbors to be considered as potential merge candidates. It is not practical to perform motion compensation and rate-distortion optimization for all possible merge candidates. To address this concern, a hardware-efficient process can be implemented to rank and select merge candidates. A reference frame priority list is applied to select a subset of potential reference frame combinations. An efficient top-K sorting algorithm is applied to identify merge candidates for each reference frame combination and keep top merge candidates with highest weights. Motion compensation and rate-distortion optimization are performed on the top merge candidates only.Type: ApplicationFiled: August 8, 2024Publication date: December 5, 2024Applicant: Intel CorporationInventors: Qian Xu, Jian Hu, Navyasree Matturu, Dmitry E. Ryzhov, Satya N. Yedidi
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Patent number: 11729416Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a residual error based on coding unit information, and determine a candidate coding unit and an associated rate distortion cost based on the residual error. An embodiment may additionally or alternatively include technology to partition a first coding unit into two or more smaller coding units based on a partition message, accelerate processing of at least one of the two or more smaller coding units, and estimate motion fora frame based at least partially on results of the accelerated processing. Other embodiments are disclosed and claimed.Type: GrantFiled: December 29, 2017Date of Patent: August 15, 2023Assignee: Intel CorporationInventors: Srinivasan Embar Raghukrishnan, James M. Holland, Sang-Hee Lee, Atthar H. Mohammed, Dmitry E. Ryzhov, Jason Tanner, Lidong Xu, Wenhao Zhang
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Publication number: 20230097092Abstract: Techniques related to video encoding include inline downscaling hardware in multi-pass encoding.Type: ApplicationFiled: November 1, 2022Publication date: March 30, 2023Applicant: Intel CorporationInventors: Shriram S. Deshpande, Satya N. Yedidi, James M. Holland, Dmitry E. Ryzhov, Jian Hu, Sai Agnihotri, Indira Munagani
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Patent number: 11323700Abstract: Example apparatus to encode video disclosed herein include an encoder to perform an intra search first stage based on source pixels of a source video frame to determine first intra candidates to predict a block of the source video frame. In disclosed examples, the encoder is also to perform an intra search second stage based on reconstructed pixels of neighboring blocks associated with the first intra candidates to determine a second intra candidate. In disclosed examples, the encoder is further to encode the block of the source video frame based on the second intra candidate.Type: GrantFiled: November 30, 2020Date of Patent: May 3, 2022Assignee: Intel CorporationInventors: James M. Holland, Srinivasan Embar Raghukrishnan, Zhijun Lei, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi
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Patent number: 11025913Abstract: A system for video encoding is described herein. The system includes a processor to execute a multi-pass palette search and mapping on a video frame to generate palette candidates. The processor is to execute an intra block copy prediction on the video frame to generate intra-block-copy candidates. The processor is to also calculate a rate distortion optimization (RDO) cost for a set of generated residuals, the palette candidates, and the intra-block-copy candidates. The processor is to further also execute a final mode decision based on a comparison of the rate distortion optimization (RDO) costs.Type: GrantFiled: May 1, 2019Date of Patent: June 1, 2021Assignee: Intel CorporationInventors: James M. Holland, Srinivasan Embar Raghukrishnan, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi, Wenhao Zhang
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Publication number: 20210084294Abstract: Example apparatus to encode video disclosed herein include an encoder to perform an intra search first stage based on source pixels of a source video frame to determine first intra candidates to predict a block of the source video frame. In disclosed examples, the encoder is also to perform an intra search second stage based on reconstructed pixels of neighboring blocks associated with the first intra candidates to determine a second intra candidate. In disclosed examples, the encoder is further to encode the block of the source video frame based on the second intra candidate.Type: ApplicationFiled: November 30, 2020Publication date: March 18, 2021Inventors: James M. Holland, Srinivasan Embar Raghukrishnan, Zhijun Lei, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi
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Patent number: 10855983Abstract: An example system includes a processor to execute an intra search first stage on a video frame to generate intra candidates. The processor is to execute an intra search second stage on the intra candidates to generate a final intra candidate and residuals. The processor is to also execute a final mode decision and generate reconstructed pixels based on the final intra candidate and the residuals.Type: GrantFiled: June 13, 2019Date of Patent: December 1, 2020Assignee: Intel CorporationInventors: James M. Holland, Srinivasan Embar Raghukrishnan, Zhijun Lei, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi
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Publication number: 20200314447Abstract: An embodiment of a semiconductor package apparatus may include technology to determine a residual error based on coding unit information, and determine a candidate coding unit and an associated rate distortion cost based on the residual error. An embodiment may additionally or alternatively include technology to partition a first coding unit into two or more smaller coding units based on a partition message, accelerate processing of at least one of the two or more smaller coding units, and estimate motion fora frame based at least partially on results of the accelerated processing. Other embodiments are disclosed and claimed.Type: ApplicationFiled: December 29, 2017Publication date: October 1, 2020Applicant: INTEL CORPORATIONInventors: Srinivas Embar Raghukrishnan, James M. Holland, Sang-Hee Lee, Atthar H. Mohammed, Dmitry E. Ryzhov, Jason Tanner, Lidong Xu, Wenhao Zhang
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Patent number: 10555002Abstract: Techniques related to long term reference picture video coding are discussed. Such techniques include determining long term reference pictures for a sequence of pictures, adjusting the quantization parameters for the long term reference pictures based on temporal correlations for pictures temporally neighboring and including the long term reference pictures, and managing reference picture lists including the long term reference pictures.Type: GrantFiled: January 21, 2016Date of Patent: February 4, 2020Assignee: Intel CorporationInventors: Ximin Zhang, Sang-Hee Lee, Dmitry E. Ryzhov
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Publication number: 20190297344Abstract: An example system includes a processor to execute an intra search first stage on a video frame to generate intra candidates. The processor is to execute an intra search second stage on the intra candidates to generate a final intra candidate and residuals. The processor is to also execute a final mode decision and generate reconstructed pixels based on the final intra candidate and the residuals.Type: ApplicationFiled: June 13, 2019Publication date: September 26, 2019Applicant: INTEL CORPORATIONInventors: James M. Holland, Srinivasan Embar Raghukrishnan, Zhijun Lei, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi
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Publication number: 20190261001Abstract: A system for video encoding is described herein. The system includes a processor to execute a multi-pass palette search and mapping on a video frame to generate palette candidates. The processor is to execute an intra block copy prediction on the video frame to generate intra-block-copy candidates. The processor is to also calculate a rate distortion optimization (RDO) cost for a set of generated residuals, the palette candidates, and the intra-block-copy candidates. The processor is to further also execute a final mode decision based on a comparison of the rate distortion optimization (RDO) costs.Type: ApplicationFiled: May 1, 2019Publication date: August 22, 2019Applicant: INTEL CORPORATIONInventors: James M. Holland, Srinivasan Embar Raghukrishnan, Dmitry E. Ryzhov, Lidong Xu, Satya N. Yedidi, Wenhao Zhang
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Patent number: 10291925Abstract: An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder includes a fixed function hierarchical motion estimation search unit, fixed function integer motion estimation search units, and a fixed function check and refinement unit. The check and refinement unit is to generate residuals using nested loops based on at least one spatial domain prediction and at least one frequency domain prediction and perform a final mode decision based on rate distortion optimization (RDO) costs associated with the generated residuals. The hardware bit packing unit is to pack bits as coded according to the final mode decision into a data format.Type: GrantFiled: July 28, 2017Date of Patent: May 14, 2019Assignee: Intel CorporationInventors: James M. Holland, Srinivasan Embar Raghukrishnan, Lidong Xu, Fangwen Fu, Dmitry E. Ryzhov, Satya N. Yedidi
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Techniques for generating wave front groups for parallel processing a video frame by a video encoder
Patent number: 10257529Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for dividing a frame comprising pixels into a number of macroblocks, each macroblock comprising a number of pixels within four macroblock boundaries. Various embodiments may also include creating at least two regions having a plurality of macroblocks by dividing the frame along macroblock boundaries and generating wave front groups based on the macroblocks in each region, each wave front group from each region comprising one or more macroblocks to process in parallel.Type: GrantFiled: June 30, 2014Date of Patent: April 9, 2019Assignee: INTEL CORPORATIONInventors: Changwon D. Rhee, Kin-Hang Cheung, Sang-Hee Lee, Zhijun Lei, Dmitry E. Ryzhov, Xinglei Zhu -
Publication number: 20190037227Abstract: An apparatus of video encoding is described herein. The apparatus includes an encoder and a hardware bit packing unit. The encoder includes a fixed function hierarchical motion estimation search unit, fixed function integer motion estimation search units, and a fixed function check and refinement unit. The check and refinement unit is to generate residuals using nested loops based on at least one spatial domain prediction and at least one frequency domain prediction and perform a final mode decision based on rate distortion optimization (RDO) costs associated with the generated residuals. The hardware bit packing unit is to pack bits as coded according to the final mode decision into a data format.Type: ApplicationFiled: July 28, 2017Publication date: January 31, 2019Applicant: Intel CorporationInventors: James M. Holland, Srinivasan Embar Raghukrishnan, Lidong Xu, Fangwen Fu, Dmitry E. Ryzhov, Satya N. Yedidi
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Patent number: 9872026Abstract: Techniques related to video coding with sample adaptive offset coding are discussed. Such techniques may include setting a sample adaptive offset coding flag for a picture of a group of pictures based at least in part on a comparison of an available coding bit limit of the picture to a first threshold and a quantization parameter of the picture to a second threshold. In some examples, such techniques may also include setting the sample adaptive offset coding flag based on a coding structure associated with coding the group of pictures.Type: GrantFiled: June 12, 2015Date of Patent: January 16, 2018Assignee: Intel CorporationInventors: Ximin Zhang, Sang-Hee Lee, Dmitry E. Ryzhov
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Publication number: 20170214938Abstract: Techniques related to long term reference picture video coding are discussed. Such techniques may include determining long term reference pictures for a sequence of pictures, adjusting the quantization parameters for the long term reference pictures, and managing reference picture lists.Type: ApplicationFiled: January 21, 2016Publication date: July 27, 2017Inventors: Ximin Zhang, Sang-Hee Lee, Dmitry E. Ryzhov
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Publication number: 20160366413Abstract: Techniques related to video coding with sample adaptive offset coding are discussed. Such techniques may include setting a sample adaptive offset coding flag for a picture of a group of pictures based at least in part on a comparison of an available coding bit limit of the picture to a first threshold and a quantization parameter of the picture to a second threshold. In some examples, such techniques may also include setting the sample adaptive offset coding flag based on a coding structure associated with coding the group of pictures.Type: ApplicationFiled: June 12, 2015Publication date: December 15, 2016Inventors: Ximin Zhang, Sang-Hee Lee, Dmitry E. Ryzhov
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Patent number: 9247256Abstract: Methods and systems may provide for utilizing a skip check module located in a video processing component to facilitate Scalable Video Coding (SVC) by determining cost relating to compression techniques. In one example, the method may include determining a location value associated with a current macro-block (MB), determining a source surface value associated with the current MB, determining a reference surface value associated with the current MB, determining a skip center value associated with the current MB, and calculating a cost value for utilizing a compression technique using the location value, the source surface value, the reference surface value, and the skip center value.Type: GrantFiled: December 19, 2012Date of Patent: January 26, 2016Assignee: Intel CorporationInventors: Zhijun Lei, Dmitry E. Ryzhov
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Publication number: 20150382021Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for divide a frame comprising pixels into a number of macroblocks, each macroblock comprising a number of pixels within four macroblock boundaries. Various embodiments may also include creating at least two regions having a plurality of macroblocks by dividing the frame along macroblock boundaries and generating wave front groups based on the macroblocks in each region, each wave front group from each region comprising one or more macroblocks to process in parallel.Type: ApplicationFiled: June 30, 2014Publication date: December 31, 2015Inventors: Changwon D. Rhee, Kin-Hang Cheung, Sang-Hee Lee, Zhijun Lei, Dmitry E. Ryzhov, Xinglei Zhu
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Publication number: 20140169470Abstract: Methods and systems may provide for utilizing a skip check module located in a video processing component to facilitate Scalable Video Coding (SVC) by determining cost relating to compression techniques. In one example, the method may include determining a location value associated with a current macro-block (MB), determining a source surface value associated with the current MB, determining a reference surface value associated with the current MB, determining a skip center value associated with the current MB, and calculating a cost value for utilizing a compression technique using the location value, the source surface value, the reference surface value, and the skip center value.Type: ApplicationFiled: December 19, 2012Publication date: June 19, 2014Inventors: Zhijun Lei, Dmitry E. Ryzhov