Patents by Inventor Dmitry G. Netis

Dmitry G. Netis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6400639
    Abstract: A memory decoder system is disclosed. In an exemplary embodiment of the invention, the system includes a matrix of memory cells, arranged into rows and columns, with a plurality of wordline drivers corresponding to each row in the matrix. A group of wordline driver-decoder blocks each contains a subset of the plurality of wordline drivers therein, with each of the wordline driver-decoder blocks being separated by a row control block. The row control block includes control circuitry for the wordline drivers. For any given wordline driver-decoder block, a first group of wordline drivers contained therein is controlled by a row control block located on one side of the given wordline driver-decoder block, while a second group of wordline drivers contained therein is controlled by a row control block located on an opposite side of the given wordline driver-decoder block.
    Type: Grant
    Filed: November 14, 2000
    Date of Patent: June 4, 2002
    Assignee: International Business Machines Corporation
    Inventors: Brian L. Ji, Toshiaki Kirihata, Dmitry G. Netis
  • Patent number: 6185135
    Abstract: A wordline activation delay monitor circuit is disclosed wherein at least one sample wordline and a sample wordline redundancy are located within the same data-storing array region of a memory, and a sample wordline selector is coupled to activate the sample wordline or sample wordline redundancy based on the state of a nonvolatile input. The wordline selector circuit may include one or both of a row decoder circuit or a wordline driver circuit which have substantially the same structure and location as row decoder circuits and wordline driver circuits used to activate wordlines within the data-storing array region.
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: February 6, 2001
    Assignee: International Business Machines Corporation
    Inventors: Dmitry G. Netis, L. Brian Ji, Toshiaki Kirihata
  • Patent number: 6115310
    Abstract: A wordline activation delay monitor circuit is disclosed herein which includes a sample wordline located within a data-storing array of a memory, wherein the sample wordline is selected or activated by circuitry having substantially the same structure or location within the memory as circuitry which selects or activates wordlines of the data-storing array. A circuit is disclosed which determines a wordline activation delay for a first subarray group within the memory by activating a sample wordline which is located within a data-storing array of a second subarray group. Corresponding methods are also disclosed.
    Type: Grant
    Filed: January 5, 1999
    Date of Patent: September 5, 2000
    Assignee: International Business Machines Corporation
    Inventors: Dmitry G. Netis, L. Brian Ji, Toshiaki Kirihata