Patents by Inventor Dmitry Korchemny
Dmitry Korchemny has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240273271Abstract: An assertion for a sequential implication for a circuit design is received. The sequential implication defines a nonoverlapping transaction in which new transactions are not allowed while an existing transaction is still pending. The assertion is converted to a deterministic finite automaton on finite words in a machine-readable form, which is made available to verify the operation of the circuit design.Type: ApplicationFiled: February 12, 2023Publication date: August 15, 2024Inventors: Dmitry Korchemny, Naphtali Yehoshua Sprei, Ilya Kudryavtsev
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Publication number: 20230214574Abstract: A directed acyclic graph (DAG) and an extended regular expression (ERE) may be received. A circuit design may be generated based on the DAG. A cover property may be generated based on the ERE. The circuit design may be simulated. A first result may be determined based on whether the cover property is satisfied during the simulating the circuit design. It may be determined whether the ERE matches a path in the DAG based on the first result.Type: ApplicationFiled: December 19, 2022Publication date: July 6, 2023Applicant: Synopsys, Inc.Inventor: Dmitry Korchemny
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Publication number: 20230017872Abstract: A system receives assertions representing properties of a circuit design. The system determines a representation of an alternating Büchi automaton based on the assertions. The system transforms the representation of the alternating Büchi automaton to generate a representation of a simplified alternating Büchi automaton. The simplified alternating Büchi automaton has fewer states than the alternating Büchi automaton. One or more states of the simplified alternating Büchi automaton are obtained by merging states of the alternating Büchi automaton representing the assertions of the circuit. The system performs formal verification of the circuit design using the simplified alternating Büchi automaton.Type: ApplicationFiled: July 7, 2022Publication date: January 19, 2023Inventors: Dmitry Korchemny, Naphtali Yehoshua Sprei
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Patent number: 11544435Abstract: The present disclosure generally relates to an analog mixed-signal (AMS) design verification system. In particular, the present disclosure relates to a system and method for system verification. One example method includes: obtaining an electronic representation of the circuit design; generating at least a portion of a waveform using the electronic representation of the circuit to obtain a first segment of the waveform associated with the circuit; converting, via the one or more processors, one or more measurement functions to code for performing the one or more computations on the first segment of the waveform; performing one or more computations on the first segment of the waveform using the code; and identifying when a behavior of the circuit violates a design specification based on whether a result of the one or more computations meets a threshold.Type: GrantFiled: June 21, 2021Date of Patent: January 3, 2023Assignee: Synopsys, Inc.Inventors: Dmitry Korchemny, Ilya Kudryavtsev, Eduard Cerny, Dmitriy Mosheyev
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Patent number: 11501050Abstract: A design for an analog mixed-signal (AMS) circuit is accessed. An assertion for verifying the behavior of an analog signal in the AMS circuit is also accessed. The assertion is expressed in an assertion language for AMS circuits. A processor verifies the assertion against the predicted behavior of the analog signal in the AMS circuit. In various embodiments, the assertion language contains predefined classes for assertions in the temporal domain, for assertions in the frequency domain, and for assertions based on functional dependencies of an output analog signal on an input analog signal.Type: GrantFiled: February 16, 2021Date of Patent: November 15, 2022Assignee: Synopsys, Inc.Inventors: Dmitry Korchemny, Eduard R. Cerny, Ilya Kudryavtsev
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Patent number: 11386250Abstract: A method of detecting a timing violation between a first sequential element and a second sequential element in a circuit design being emulated in a hardware emulation system includes, in part, determining a timing relationship between first and second clocks applied respectively to the first sequential element and the second sequential element, reconfiguring a combinational logic disposed between the first sequential element and the second sequential element as one or more buffers, setting a delay across the one or more buffers to one or more clock cycles of the hardware emulation system based on the timing relationship, reprogramming the first and second clocks in accordance with the delay, and detecting a timing violation if a change in an output of the first flip-flop is not stored in the second flip-flop within the delay.Type: GrantFiled: January 26, 2021Date of Patent: July 12, 2022Assignee: Synopsys, Inc.Inventors: Dmitry Korchemny, Nathaniel Azuelos, Boris Gommershtadt, Alexander Shot
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Patent number: 11232174Abstract: Techniques and systems for solving Boolean satisfiability (SAT) problems are described. Some embodiments solve SAT problems using efficient construction of truth tables. Some embodiments can improve performance of SAT solvers by using truth tables instead of incurring the overhead of Conjunctive Normal Form (CNF) conversion.Type: GrantFiled: September 12, 2019Date of Patent: January 25, 2022Assignee: Synopsys, Inc.Inventor: Dmitry Korchemny
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Patent number: 11188695Abstract: Synthesis of functional coverage (e.g., covergroups) is optimized for hardware emulation. The optimization may reduce the number of logic gates used to implement the hardware emulator circuits or reduce the computer resources used to synthesize the hardware emulator circuits. The optimization may also prevent the synthesis of unnecessary circuits. In another aspect, the optimization may result in a representation that may be used both to synthesize hardware emulation circuits and as part of formal verification. This may result in a model that can be used for formal verification, hardware emulation, and software simulation.Type: GrantFiled: August 8, 2018Date of Patent: November 30, 2021Assignee: Synopsys, Inc.Inventors: Dmitry Korchemny, Ashok Kumar Bhatt, Eduard Rudolf Cerny, Hanish Singla
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Patent number: 11176293Abstract: The independent claims of this patent signify a concise description of embodiments. A method is provided for reducing a size of an emulation clock tree for a circuit design. The method comprises identifying a fan-in cone of an input of a sequential element of the circuit design; identifying one or more fan-in cone sequential elements which do not directly affect the input of the sequential element; and removing the one or more identified fan-in cone sequential elements of the fan-in cone from the emulation clock tree. This Abstract is not intended to limit the scope of the claims.Type: GrantFiled: March 7, 2019Date of Patent: November 16, 2021Assignee: Synopsys, Inc.Inventors: Dmitry Korchemny, Alexander Rabinovitch, Boris Gommershtadt, Daniel Geist, Srivatsan Raghavan
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Publication number: 20210232742Abstract: A method of detecting a timing violation between a first sequential element and a second sequential element in a circuit design being emulated in a hardware emulation system includes, in part, determining a timing relationship between first and second clocks applied respectively to the first sequential element and the second sequential element, reconfiguring a combinational logic disposed between the first sequential element and the second sequential element as one or more buffers, setting a delay across the one or more buffers to one or more clock cycles of the hardware emulation system based on the timing relationship, reprogramming the first and second clocks in accordance with the delay, and detecting a timing violation if a change in an output of the first flip-flop is not stored in the second flip-flop within the delay.Type: ApplicationFiled: January 26, 2021Publication date: July 29, 2021Inventors: Dmitry Korchemny, Nathaniel Azuelos, Boris Gommershtadt, Alexander Shot
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Patent number: 10962595Abstract: Coverage event counters for hardware verification emulations are implemented as linear feedback shift register-based counters generating encoded counter values indicative of a detected number of coverage events. To decode those counter values, a counter algorithm utilized to generate the encoded counter value may continue to be iterated after counting is complete until reaching a defined pattern, while counting the number of iterations (K) necessary to reach the defined pattern. The resulting counter value having the defined pattern is correlated with a mapping table to identify a numerical value, and an ordinal counter value indicative of the number of coverage events is determined based on the identified numerical value, less K.Type: GrantFiled: November 15, 2018Date of Patent: March 30, 2021Assignee: SYNOPSYS, INC.Inventors: Leonid Alexander Broukhis, Boris Gommershtadt, Florent Duru, Gabriel Gouvine, Dmitry Korchemny
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Patent number: 10579760Abstract: Forming a logic circuit design from a behavioral description language that includes N force and M release statements applied to a net disposed in the design, includes, in part, forming N multiplexers and a controller controlling the select terminals of the N multiplexers. Each multiplexer receives a force signal at its first input terminal. The output signal of the ith multiplexer is supplied to a second input terminal of (i+1)th multiplexer. A driver signal driving the net in the absence of the force statements is applied to a second input terminal of a first multiplexer. The controller asserts the select signal of the ith multiplexer if the ith force condition is active, and unasserts the select signal of the ith multiplexer if any one of a number of predefined conditions is satisfied.Type: GrantFiled: October 29, 2018Date of Patent: March 3, 2020Assignee: SYNOPSYS, INC.Inventors: Ionut Silviu Cirjan, Boris Gommershtadt, Dmitry Korchemny, Naphtali Yehoshua Sprei
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Publication number: 20200034499Abstract: Forming a logic circuit design from a behavioral description language that includes N force and M release statements applied to a net disposed in the design, includes, in part, forming N multiplexers and a controller controlling the select terminals of the N multiplexers. Each multiplexer receives a force signal at its first input terminal. The output signal of the ith multiplexer is supplied to a second input terminal of (i+1)th multiplexer. A driver signal driving the net in the absence of the force statements is applied to a second input terminal of a first multiplexer. The controller asserts the select signal of the ith multiplexer if the ith force condition is active, and unasserts the select signal of the ith multiplexer if any one of a number of predefined conditions is satisfied.Type: ApplicationFiled: October 29, 2018Publication date: January 30, 2020Inventors: Ionut Silviu Cirjan, Boris Gommershtadt, Dmitry Korchemny, Naphtali Yehoshua Sprei
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Publication number: 20190050516Abstract: Synthesis of functional coverage (e.g., covergroups) is optimized for hardware emulation. The optimization may reduce the number of logic gates used to implement the hardware emulator circuits or reduce the computer resources used to synthesize the hardware emulator circuits. The optimization may also prevent the synthesis of unnecessary circuits. In another aspect, the optimization may result in a representation that may be used both to synthesize hardware emulation circuits and as part of formal verification. This may result in a model that can be used for formal verification, hardware emulation, and software simulation.Type: ApplicationFiled: August 8, 2018Publication date: February 14, 2019Inventors: Dmitry Korchemny, Ashok Kumar Bhatt, Eduard Rudolf Cerny, Hanish Singla