Patents by Inventor Dmitry Messerman

Dmitry Messerman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7389001
    Abstract: Scanning a layer of a layout in a first direction and selecting a first rectangle in a scan order, scanning the layer of the layout in a second direction orthogonal to the first direction to find a second rectangle that intersects the first rectangle, and if the second rectangle is found, performing a union of the first and second rectangles to generate a set of non-intersecting rectangles equivalent to the first and second rectangle.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: June 17, 2008
    Assignee: Intel Corporation
    Inventors: Dmitry Messerman, Michael Seltser
  • Patent number: 7325208
    Abstract: Embodiments of the present invention provide a method, apparatus and system for inductance modeling. According to some exemplary embodiments, a method for inductance modeling may include determining a plurality of two-dimensional mutual inductance values corresponding to a designated victim within a geometrical event and a plurality of designated attackers, respectively. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: January 29, 2008
    Assignee: Intel Corporation
    Inventors: Sourav Chakravarty, Yaakov Ben-Noon, Eli Chiprout, Mohiuddin Mazumder, Dmitry Messerman
  • Publication number: 20060074617
    Abstract: Embodiments of the present invention provide a method, apparatus and system for inductance modeling. According to some exemplary embodiments, a method for inductance modeling may include determining a plurality of two-dimensional mutual inductance values corresponding to a designated victim within a geometrical event and a plurality of designated attackers, respectively. Other embodiments are described and claimed.
    Type: Application
    Filed: September 28, 2004
    Publication date: April 6, 2006
    Inventors: Sourav Chakravarty, Yaakov Ben-Noon, Eli Chiprout, Mohiuddin Mazumder, Dmitry Messerman
  • Publication number: 20050149889
    Abstract: Scanning a layer of a layout in a first direction and selecting a first rectangle in a scan order, scanning the layer of the layout in a second direction orthogonal to the first direction to find a second rectangle that intersects the first rectangle, and if the second rectangle is found, performing a union of the first and second rectangles to generate a set of non-intersecting rectangles equivalent to the first and second rectangle.
    Type: Application
    Filed: December 18, 2003
    Publication date: July 7, 2005
    Inventors: Dmitry Messerman, Michael Seltser
  • Patent number: 5943487
    Abstract: A method for extracting a reduced resistor network from an integrated circuit polygon layout is disclosed. The polygon layout includes a Manhattan polygon defined by a plurality of boundary lines. The method involves fracturing the Manhattan polygon along first and second division lines which extend from an intersection point at which first and second boundary lines intersect to define a 270 degree angle within the polygon. The first and second division lines extend parallel to the first and second boundary lines respectively and traverse the polygon so as to fracture the polygon into a number of rectangles. Each rectangle is substituted, or modeled, with a star configuration resistor arrangement, so as to construct a full resistor network. The method then enters an iterative sequence in which network reduction opportunities within the full resistor network are identified, and data concerning each network reduction opportunity is stored.
    Type: Grant
    Filed: July 12, 1996
    Date of Patent: August 24, 1999
    Assignee: Intel Corporation
    Inventors: Dmitry Messerman, Gershon Hochman