Abstract: Methods and apparatus for implementing a programmable integrated circuit using circuit design tools are provided. The circuit design tools may receive a high-level synthesis source code, parse the high-level synthesis source code to generate a compiler intermediate representation, process the compiler intermediate representation to generate a register transfer level (RTL) description, and then synthesize and compile the RTL description to generate an output netlist. Timing analysis may be performed on the output netlist to identify a critical path. Components in the critical path may be mapped back to specific portions in the RTL descriptions, to specification portions of the compiler intermediate representation, and to specific lines in the high-level synthesis source code. The designer can then optimize the high-level synthesis source code to shorten the critical path. This process may be iterated as many times as desired.

Abstract: Integrated circuits with digital signal processing (DSP) blocks are provided. A DSP block may include one or more large multiplier circuits. A large multiplier circuit (e.g., an 18×18 or 18×19 multiplier circuit) may be used to support two or more smaller multiplication operations sharing one or two sets of multiplier operands, a complex multiplication, and a sum of two multiplications. If the multiplier products overflow and interfere with one another, correction operations can be performed. Partial products from two or more larger multiplier circuits can be used to combine decomposed partial products. A large multiplier circuit can also be used to support two floating-point mantissa multipliers.

Abstract: A method for designing a system on a target device includes performing a high-level compilation of a computer program language description of the system to generate a hardware description language (HDL) of the system. The high-level compilation performs optimizations in response to profile data obtained from an earlier compilation of the system.

Abstract: A method for designing a system on a target device includes performing a high-level compilation of a computer program language description of the system to generate a hardware description language (HDL) of the system. The high-level compilation performs optimizations in response to profile data obtained from an earlier compilation of the system.

Abstract: A method for performing a high-level compilation of a computer program language (CPL) description of a system to generate a hardware description language (HDL) of the system includes inserting one or more compression/decompression units into the HDL in response to detecting a user inserted term in a kernel definition of an argument in the CPL description to indicate that the argument requires compression.

Abstract: Methods and apparatus for implementing a programmable integrated circuit using circuit design tools are provided. The circuit design tools may receive a high-level synthesis source code, parse the high-level synthesis source code to generate a compiler intermediate representation, process the compiler intermediate representation to generate a register transfer level (RTL) description, and then synthesize and compile the RTL description to generate an output netlist. Timing analysis may be performed on the output netlist to identify a critical path. Components in the critical path may be mapped back to specific portions in the RTL descriptions, to specification portions of the compiler intermediate representation, and to specific lines in the high-level synthesis source code. The designer can then optimize the high-level synthesis source code to shorten the critical path. This process may be iterated as many times as desired.

Abstract: Integrated circuits with digital signal processing (DSP) blocks are provided. A DSP block may include one or more large multiplier circuits. A large multiplier circuit (e.g., an 18×18 or 18×19 multiplier circuit) may be used to support two or more smaller multiplication operations sharing one or two sets of multiplier operands, a complex multiplication, and a sum of two multiplications. If the multiplier products overflow and interfere with one another, correction operations can be performed. Partial products from two or more larger multiplier circuits can be used to combine decomposed partial products. A large multiplier circuit can also be used to support two floating-point mantissa multipliers.

Abstract: An integrated circuit with optical flow computation circuitry is provided. The optical flow computation circuitry may include a first image shift register for receiving pixel values from a current video frame, a second image shift register for receiving pixel values from a previous video frame, column shift registers for storing column sums of various gradient-based values, square sum registers for storing square sums generated at least partly based on the column sum values, and an associated computation circuit that constructs a gradient matrix based on values stored in the square sum registers and that computes a 2-dimensional optical flow vector based on an inverse of the gradient matrix and differences between the current and previous frames. Optical flow computing circuitry configured in this way may be capable of supporting dense optical flow calculation for at least one pixel per clock cycle while supporting large window sizes.

Abstract: A method of programming or configuring an integrated circuit device using a high-level language includes parsing a logic flow to be embodied in the integrated circuit device to identify invariant logic flow, converting the invariant logic flow into separate instruction blocks, incorporating the separate instruction blocks into a high-level language representation of a configuration of resources of the integrated circuit device, and compiling the high-level language representation to configure said integrated circuit device. The high-level language representation can be executed to generate a configuration bitstream for the programmable integrated circuit device, or can be run on a processor on the programmable integrated circuit device to instantiate the configuration.

Abstract: A method of programming or configuring an integrated circuit device using a high-level language includes parsing a logic flow to be embodied in the integrated circuit device to identify branching control flow, converting the branching control flow into predicated instructions, incorporating the predicated instructions into a high-level language representation of a configuration of resources of the integrated circuit device, and compiling the high-level language representation to configure said integrated circuit device. The high-level language representation can be executed to generate a configuration bitstream for the programmable integrated circuit device, or can be run on a processor on the programmable integrated circuit device to instantiate the configuration.