Abstract: A power amplifier (100) suitable for use in mobile telecommunications equipment has a first stage (2) and an optional second stage (2), each stage being provided with a bias circuit (4, 5). To provide a well-defined gain characteristic, in the first stage (1) a bias current (Ib1) is fed into a signal amplifying transistor (T1). The first bias circuit (4) comprises non-linear a voltage/current converter (41) coupled to a current mirror (40). To suit alternative applications, such as GSM and UMTS requiring a different bias, plural voltage/current converters (41, 42) may be provided in parallel.

Abstract: A detection circuit for detecting the output power of a power amplifier comprises a first current minor transistor (Ti 1) having a base, which is connectable to a power transistor (T10), and a collector, a RF detection means (RF-det) for detecting the RF current flowing through the current mirror transistor (T11). Said RF detection means (RFdet) is connected to the collector of said first current mirror transistor (T11). Said detection circuit further comprises a biasing means (bias-RF-det) for biasing said RF detection means (RF-det), wherein said biasing means is connected to said collector of said first current mirror (T11) and said RF detection means (RF-det).

Abstract: A RF power amplifier circuit has at least one power transistor and a protection circuit protecting the power transistor against high voltages that lead to a destructive breakdown of the transistor. The circuit comprises a power transistor (2), a biasing circuit (6) biasing the power transistor; a peak detector (8) measuring the output voltage of the power transistor; and a comparator circuit (12) connected to the peak detector (8) and designed to reduce the base current of the power transistor (2) when controlled by the peak detector (8).

Abstract: A RF power amplifier circuit has at least one power transistor and a protection circuit protecting the power transistor against high voltages that lead to a destructive breakdown of the transistor. The circuit comprises a power transistor (2), a biasing circuit (6) biasing the power transistor; a peak detector (8) measuring the output voltage of the power transistor; and a comparator circuit (12) connected to the peak detector (8) and designed to reduce the base current of the power transistor (2) when controlled by the peak detector (8).