Abstract: Disclosed is a method comprising receiving, from a first transmission and reception point of a wireless communication network, an indication for transmitting a random-access preamble to a second transmission and reception point of the wireless communication network after a beam switch from a source beam of the first transmission and reception point to a target beam of the second transmission and reception point; and transmitting the random-access preamble to the second transmission and reception point after the beam switch.

Abstract: Example embodiments of the present disclosure relate to timing adjustment for uplink transmission, particularly in a high-speed scenario. A first device receives, from a second device, offset information indicating a difference in propagation delays between the first device and a third device experienced by the second device. The offset information is determined based on a time shifting value for a range of the difference in propagation delays. The time shifting value is associated with a switch from a beam associated with the first device to a beam associated with the third device. The third device is different from the first device. The first device transmits, to the second device, timing information indicating an amount of timing advance for transmission from the second device to the third device. The timing information is determined based on the time shifting value. Through this solution. UL transmission will be timing aligned.

Abstract: The invention relates to a construction foil (16), especially roof film, roofing foil, flat roof sheeting, fa-cade sheeting and/or vapor barrier and/or sub-roofing sheeting, especially underlayment and/or sarking sheeting, with a single- or multilayer layer structure (17). It is provided according to the invention that at least one moisture sensor (1) for detecting moisture is associated to the construction foil (16), that the moisture sensor (1) is designed as an active pick-up, and that the moisture sensor (1) comprises at least one electrode (18) and/or a humidity sensing element, and the electrode (18) and/or the humidity sensing element is in direct contact with a nonwoven layer (19).

Abstract: Methods, apparatuses, and computer program products for uplink (UL) timing advance (TA) adjustment at beam switch are provided. A method may include, when it is determined that beam change or transmission configuration indication (TCI) state switch should occur for beam(s) originating from non-collocated source nodes, enabling assistance information relating to time difference for a UE. The method may include preparing timing adjustment prediction model(s) configured to predict a timing advance adjustment (TAA) or actual TA that should be applied by the UE at the beam change, using the at least one prepared timing adjustment prediction model to determine the TAA or the actual TA that should be applied by the UE at the beam change. The method may include signaling or assigning the TAA or the actual TA to the UE, or using the TAA to adjust for a UE autonomously adjusted TA value at the beam change.

Abstract: The disclosed systems, structures, and methods are directed to a low jitter phase-lock loop (PLL) based frequency synthesizer, comprising a first frequency divider, a phase frequency detector, a charge pump, a low-pass filter, a voltage control oscillator (VCO), a phase interpolator communicatively coupled in a feedback path between the VCO and the phase frequency detector, wherein the phase interpolator comprises a quadrature generator, an input conditioner, a phase rotator, a current mode logic (CML), and a second frequency divider communicatively coupled in the feedback path between the phase interpolator and the phase frequency detector.

Abstract: The disclosed systems, structures, and methods are directed to a low jitter phase-lock loop (PLL) based frequency synthesizer, comprising a first frequency divider, a phase frequency detector, a charge pump, a low-pass filter, a voltage control oscillator (VCO), a phase interpolator communicatively coupled in a feedback path between the VCO and the phase frequency detector, wherein the phase interpolator comprises a quadrature generator, an input conditioner, a phase rotator, a current mode logic (CML), and a second frequency divider communicatively coupled in the feedback path between the phase interpolator and the phase frequency detector.

Abstract: The invention relates to a construction foil (16), especially roof film, roofing foil, flat roof sheeting, fa-cade sheeting and/or vapor barrier and/or sub-roofing sheeting, especially underlayment and/or sarking sheeting, with a single- or multilayer layer structure (17). It is provided according to the invention that at least one moisture sensor (1) for detecting moisture is associated to the construction foil (16), that the moisture sensor (1) is designed as an active pick-up, and that the moisture sensor (1) comprises at least one electrode (18) and/or a humidity sensing element, and the electrode (18) and/or the humidity sensing element is in direct contact with a nonwoven layer (19).

Abstract: An integrated circuit is described. The integrated circuit includes a first layer, a first clock line for carrying a first clock signal, and a second clock line for carrying a second clock signal. The second clock line runs alongside the first clock line for a distance. The integrated circuit includes a shield structure for shielding the clock line from crosstalk and/or other interference. The shield structure includes a shield wall extending from the first layer. The shield wall runs between the first and second clock lines for at least a portion of the distance. The shield structure may also include a shield cage extending from the first layer and surrounding the first and second clock lines for at least a portion of the distance. The shield cage has a plurality of openings. The shield cage and/or shield wall may be connected to the ground of an AC power supply.

Abstract: There is provided a method comprising: causing an attempt to transmit discovery signal by an access point in a first discovery window, said access point having a discovery window schedule for the transmission of a plurality of respective discovery signals; and in response to successfully transmitting the discovery signal, causing at least one subsequent discovery window in said schedule to be used for data transmission or to be unused, instead of attempting to transmit a discovery signal.

Abstract: According to a first example aspect there is provided a charge pump circuit that includes a first chopper circuit configured to switch first and second chopper circuit outputs between first and second chopper circuit inputs at a chopping frequency, wherein successive input signals at the first chopper circuit input are output alternatively at the first and second chopper circuit outputs in successive cycles of the chopping frequency and successive input signals at the second chopper circuit input are output alternatively at the second and first chopper circuit outputs in successive cycles of the chopping frequency. A differential charge pump is configured to receive the signals output from the first and second chopper circuit outputs and produce corresponding first and second charge pumped signals.

Abstract: An integrated circuit is described. The integrated circuit includes a first layer, a first clock line for carrying a first clock signal, and a second clock line for carrying a second clock signal. The second clock line runs alongside the first clock line for a distance. The integrated circuit includes a shield structure for shielding the clock line from crosstalk and/or other interference. The shield structure includes a shield wall extending from the first layer. The shield wall runs between the first and second clock lines for at least a portion of the distance. The shield structure may also include a shield cage extending from the first layer and surrounding the first and second clock lines for at least a portion of the distance. The shield cage has a plurality of openings. The shield cage and/or shield wall may be connected to the ground of an AC power supply.

Abstract: According to a first example aspect there is provided a charge pump circuit that includes a first chopper circuit configured to switch first and second chopper circuit outputs between first and second chopper circuit inputs at a chopping frequency, wherein successive input signals at the first chopper circuit input are output alternatively at the first and second chopper circuit outputs in successive cycles of the chopping frequency and successive input signals at the second chopper circuit input are output alternatively at the second and first chopper circuit outputs in successive cycles of the chopping frequency. A differential charge pump is configured to receive the signals output from the first and second chopper circuit outputs and produce corresponding first and second charge pumped signals.

Abstract: The phase-lock loop (PLL) can include a variable frequency oscillator adjustable to control the phase of the output signal; a primary control subsystem including a phase detector and a connection between the output signal and the phase detector, the phase detector generating a primary control signal to adjust the variable frequency oscillator; and a secondary control subsystem having an analog-to-digital converter and a digital-to-analog converter connected in series to receive the primary control signal and generate a secondary control signal also connected to independently adjust the variable frequency oscillator.

Abstract: The phase-lock loop (PLL) can include a variable frequency oscillator adjustable to control the phase of the output signal; a primary control subsystem including a phase detector and a connection between the output signal and the phase detector, the phase detector generating a primary control signal to adjust the variable frequency oscillator; and a secondary control subsystem having an analog-to-digital converter and a digital-to-analog converter connected in series to receive the primary control signal and generate a secondary control signal also connected to independently adjust the variable frequency oscillator.

Abstract: A method and voltage regulator comprises a generator that generates an error difference between a reference and regulated voltage. A clocked ADC samples the voltage as a digital stream. A DAC converts the stream to analog signal(s). A current source driven by the signal(s) generate(s) the regulated voltage. The generator may be an op-amp or comparator comprising a buffer and/or a latch. The N-bit ADC may be a ?-? modulator or N 1-bit ADC latches. The N-bit DAC may comprise 1-bit DACs comprising a switched-capacitor summer and a one stage RC LPF. Sampling the error up-converts flicker noise to the clock frequency which the DAC filters out. The current source may comprise N transistors with gates driven by a signal and sources tied to an independent power supply. Each signal may be weighted by a DAC weight. The apparatus may comprise a decoupling capacitor between the regulated voltage and ground.

Abstract: A method and voltage regulator comprises a generator that generates an error difference between a reference and regulated voltage. A clocked ADC samples the voltage as a digital stream. A DAC converts the stream to analog signal(s). A current source driven by the signal(s) generate(s) the regulated voltage. The generator may be an op-amp or comparator comprising a buffer and/or a latch. The N-bit ADC may be a ?-? modulator or N 1-bit ADC latches. The N-bit DAC may comprise 1-bit DACs comprising a switched-capacitor summer and a one stage RC LPF. Sampling the error up-converts flicker noise to the clock frequency which the DAC filters out. The current source may comprise N transistors with gates driven by a signal and sources tied to an independent power supply. Each signal may be weighted by a DAC weight. The apparatus may comprise a decoupling capacitor between the regulated voltage and ground.

Abstract: Methods and apparatus relating squelch filtration to limit false wakeups are described. In one embodiment, a squelch logic generates a wakeup event for an agent based on occurrence of a number of pulses (originating from another agent) during a time period. Other embodiments are also disclosed.

Abstract: A circuit comprising a loop filter, wherein the filter comprises an active integrator configured to generate one or more tuning signals, and a voltage-controlled oscillator (VCO) coupled to the loop filter and configured to generate a feedback signal based on the one or more tuning signals, wherein generating the one or more tuning signals is based on the feedback signal.

Abstract: Methods and apparatus relating squelch filtration to limit false wakeups are described. In one embodiment, a squelch logic generates a wakeup event for an agent based on occurrence of a number of pulses (originating from another agent) during a time period. Other embodiments are also disclosed.

Abstract: Apparatuses, methods, and articles of manufacture disclosing a filter with a plurality of convolver branches are described herein. Each of the plurality of convolver branches include a multiplier, integrator, and sampler and hold circuit. A sampled output of one branch may be fed back to another branch. Other embodiments may be described and claimed.