Patents by Inventor Dmitry Pidan
Dmitry Pidan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220237343Abstract: A system and method for determining concrete instances in traffic scenarios are provided. The method includes receiving a scenario in a scenario description language, wherein the scenario includes at least one sub-scenario; identifying at least one variable for the scenario and the at least one sub-scenario based on parsing of at least one actor and the received scenario; identifying at least one constraint relation derived from the scenario and the at least a sub-scenario; generating, from the at least one variable and at least one constraint, a constraint satisfaction problem; processing the constraint satisfaction problem to generate sequences of states for the at least one variable that comply with the at least one constraint, wherein the sequence of states defines the behavior of the at least one actor with time values; and determining at least one solution that includes the sequences of states.Type: ApplicationFiled: December 28, 2021Publication date: July 28, 2022Applicant: Foretellix Ltd.Inventors: Dmitry PIDAN, Cynthia Roxana DISENFELD, Yoav HOLLANDER
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Patent number: 10503633Abstract: Method, apparatus and product for symbolic execution of alternative branches. The method comprising reaching, during symbolic execution of a Control Flow Graph (CFG) of a program, a branching node in the CFG with a first symbolic state, wherein the branching has at least a first branch and a second branch, wherein the first and second branches end at a joining node in the CFG. The method further comprises symbolically executing the first branch using the first symbolic state so as to determine a second symbolic state. The method further comprises symbolically executing the second branch using the second symbolic state so as to determine a third symbolic state. Accordingly, the third symbolic state is based on sequential symbolic execution of alternative branches.Type: GrantFiled: March 30, 2016Date of Patent: December 10, 2019Assignee: International Business Machines CorporationInventors: Dmitry Pidan, Tatyana Veksler
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Patent number: 9898395Abstract: According to one exemplary embodiment, a method for preparing a software component for verification is provided. The method may include receiving the software component and a design model. The method may also include generating a wrapper program based on the received software component and the received design model. The method may then include associating the received software component with the generated wrapper program. The method may further include determining a plurality of inputs for the received software component based on the received design model. The method may also include sending the determined plurality of inputs and the received software component with associated wrapper program to a verification tool.Type: GrantFiled: January 9, 2017Date of Patent: February 20, 2018Assignee: International Business Machines CorporationInventors: Allon Adir, Fady Copty, Dmitry Pidan, Tamer Salman
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Patent number: 9875175Abstract: According to one exemplary embodiment, a method for preparing a software component for verification is provided. The method may include receiving the software component and a design model. The method may also include generating a wrapper program based on the received software component and the received design model. The method may then include associating the received software component with the generated wrapper program. The method may further include determining a plurality of inputs for the received software component based on the received design model. The method may also include sending the determined plurality of inputs and the received software component with associated wrapper program to a verification tool.Type: GrantFiled: September 25, 2015Date of Patent: January 23, 2018Assignee: International Business Machines CorporationInventors: Allon Adir, Fady Copty, Dmitry Pidan, Tamer Salman
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Patent number: 9870313Abstract: According to one exemplary embodiment, a method for preparing a software component for verification is provided. The method may include receiving the software component and a design model. The method may also include generating a wrapper program based on the received software component and the received design model. The method may then include associating the received software component with the generated wrapper program. The method may further include determining a plurality of inputs for the received software component based on the received design model. The method may also include sending the determined plurality of inputs and the received software component with associated wrapper program to a verification tool.Type: GrantFiled: January 9, 2017Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Allon Adir, Fady Copty, Dmitry Pidan, Tamer Salman
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Publication number: 20170286271Abstract: Method, apparatus and product for symbolic execution of alternative branches. The method comprising reaching, during symbolic execution of a Control Flow Graph (CFG) of a program, a branching node in the CFG with a first symbolic state, wherein the branching has at least a first branch and a second branch, wherein the first and second branches end at a joining node in the CFG. The method further comprises symbolically executing the first branch using the first symbolic state so as to determine a second symbolic state. The method further comprises symbolically executing the second branch using the second symbolic state so as to determine a third symbolic state.Type: ApplicationFiled: March 30, 2016Publication date: October 5, 2017Inventors: Dmitry Pidan, Tatyana Veksler
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Publication number: 20170109255Abstract: According to one exemplary embodiment, a method for preparing a software component for verification is provided. The method may include receiving the software component and a design model. The method may also include generating a wrapper program based on the received software component and the received design model. The method may then include associating the received software component with the generated wrapper program. The method may further include determining a plurality of inputs for the received software component based on the received design model. The method may also include sending the determined plurality of inputs and the received software component with associated wrapper program to a verification tool.Type: ApplicationFiled: January 9, 2017Publication date: April 20, 2017Inventors: Allon Adir, Fady Copty, Dmitry Pidan, Tamer Salman
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Publication number: 20170109254Abstract: According to one exemplary embodiment, a method for preparing a software component for verification is provided. The method may include receiving the software component and a design model. The method may also include generating a wrapper program based on the received software component and the received design model. The method may then include associating the received software component with the generated wrapper program. The method may further include determining a plurality of inputs for the received software component based on the received design model. The method may also include sending the determined plurality of inputs and the received software component with associated wrapper program to a verification tool.Type: ApplicationFiled: January 9, 2017Publication date: April 20, 2017Inventors: Allon Adir, Fady Copty, Dmitry Pidan, Tamer Salman
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Publication number: 20170091068Abstract: According to one exemplary embodiment, a method for preparing a software component for verification is provided. The method may include receiving the software component and a design model. The method may also include generating a wrapper program based on the received software component and the received design model. The method may then include associating the received software component with the generated wrapper program. The method may further include determining a plurality of inputs for the received software component based on the received design model. The method may also include sending the determined plurality of inputs and the received software component with associated wrapper program to a verification tool.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Inventors: Allon Adir, Fady Copty, Dmitry Pidan, Tamer Salman
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Publication number: 20170091081Abstract: According to one exemplary embodiment, a method for preparing a software component for verification is provided. The method may include receiving the software component and a design model. The method may also include generating a wrapper program based on the received software component and the received design model. The method may then include associating the received software component with the generated wrapper program. The method may further include determining a plurality of inputs for the received software component based on the received design model. The method may also include sending the determined plurality of inputs and the received software component with associated wrapper program to a verification tool.Type: ApplicationFiled: March 8, 2016Publication date: March 30, 2017Inventors: Allon Adir, Fady Copty, Dmitry Pidan, Tamer Salman
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Patent number: 9588877Abstract: According to one exemplary embodiment, a method for preparing a software component for verification is provided. The method may include receiving the software component and a design model. The method may also include generating a wrapper program based on the received software component and the received design model. The method may then include associating the received software component with the generated wrapper program. The method may further include determining a plurality of inputs for the received software component based on the received design model. The method may also include sending the determined plurality of inputs and the received software component with associated wrapper program to a verification tool.Type: GrantFiled: March 8, 2016Date of Patent: March 7, 2017Assignee: International Business Machines CorporationInventors: Allon Adir, Fady Copty, Dmitry Pidan, Tamer Salman
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Patent number: 9389984Abstract: A method, system and product for directing verification towards bug-prone portions. The method comprising syntactically analyzing a computer program to identify portions of the computer program that correspond to one or more bug patterns; and performing verification of the computer program, wherein the verification comprises traversing a control flow graph of the computer program and tracking symbolic values of variables of the computer program, wherein said performing comprises directing the traversal of the control flow graph to nodes of the control flow graph that correspond to the identified portions, whereby bug-prone portions of the computer program are prioritized to be verified before non-bug-prone portions of the computer program.Type: GrantFiled: September 10, 2013Date of Patent: July 12, 2016Assignee: International Business Machines CorporationInventors: Hana Chockler, Oded Margalit, Dmitry Pidan, Sitvanit Ruah
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Publication number: 20150074651Abstract: A method, system and product for directing verification towards bug-prone portions. The method comprising syntactically analyzing a computer program to identify portions of the computer program that correspond to one or more bug patterns; and performing verification of the computer program, wherein the verification comprises traversing a control flow graph of the computer program and tracking symbolic values of variables of the computer program, wherein said performing comprises directing the traversal of the control flow graph to nodes of the control flow graph that correspond to the identified portions, whereby bug-prone portions of the computer program are prioritized to be verified before non-bug-prone portions of the computer program.Type: ApplicationFiled: September 10, 2013Publication date: March 12, 2015Applicant: International Business Machines CorporationInventors: HANA CHOCKLER, ODED MARGALIT, DMITRY PIDAN, SITVANIT RUAH
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Publication number: 20150074652Abstract: A method, apparatus, and product for avoiding similar counter-examples in model checking. One method comprises model checking of a program by traversing control flow paths of the program to determine states associated with execution of the program, each state comprises at least symbolic values of variables; said traversing is biased to give preference to traversing control flow paths that are substantially different than control flow paths associated with traces of the program; whereby said model checking is guided away from executions that are similar to the traces. A second method comprises obtaining a counter-example produced by a model checker, computing a distance between a control flow path of the counter-example and between a set of one or more control flow paths of additional counter-examples; and in response to the distance being below a threshold, dropping the counter-example.Type: ApplicationFiled: September 10, 2013Publication date: March 12, 2015Applicant: International Business Machines CorporationInventors: HANA CHOCKLER, ODED MARGALIT, DMITRY PIDAN, SITVANIT RUAH
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Patent number: 8856755Abstract: A method, apparatus and product for dominant state based coverage metric. The method comprising: determining whether all possible states of a computer program were examined based on an analysis of states that were examined excluding controlled states that are dominated by a self-dominating states; wherein the controlled states are associated with a controlled nodes in a control flow graph of the computer program, wherein the self-dominating states are associated with a self-dominating node in the control flow graph; wherein each execution path in the control flow graph that reaches the controlled nodes also includes the self-dominating node; and wherein there exists an execution path in the control flow graph that both starts and ends at the self-dominating node and further includes at least one controlled node.Type: GrantFiled: January 27, 2013Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventors: Hana Chockler, Dmitry Pidan, Sitvanit Ruah, Karen Yorav
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Publication number: 20140215445Abstract: A method, apparatus and product for dominant state based coverage metric. The method comprising: determining whether all possible states of a computer program were examined based on an analysis of states that were examined excluding controlled states that are dominated by a self-dominating states; wherein the controlled states are associated with a controlled nodes in a control flow graph of the computer program, wherein the self-dominating states are associated with a self-dominating node in the control flow graph; wherein each execution path in the control flow graph that reaches the controlled nodes also includes the self-dominating node; and wherein there exists an execution path in the control flow graph that both starts and ends at the self-dominating node and further includes at least one controlled node.Type: ApplicationFiled: January 27, 2013Publication date: July 31, 2014Applicant: International Business Machines CorporationInventors: Hana Chockler, Dmitry Pidan, Sitvanit Ruah, Karen Yorav
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Patent number: 8219376Abstract: A computer-implemented method for verifying a design includes representing a verification directive, which pertains to the design and includes a local variable, by a finite state machine. The state machine includes multiple states, with transitions among the states, transition conditions associated with the transitions, and procedural blocks, which correspond to the transitions and define operations to be performed on the local variable when traversing the respective transitions. The finite state machine is executed by traversing the transitions in accordance with the respective transition conditions and modifying the local variable in accordance with the respective procedural blocks of the traversed transitions, so as to verify the design with respect to the verification directive.Type: GrantFiled: February 27, 2008Date of Patent: July 10, 2012Assignee: International Business Machines CorporationInventors: Dmitry Pidan, Sitvanit Ruah
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Publication number: 20090216513Abstract: A computer-implemented method for verifying a design includes representing a verification directive, which pertains to the design and includes a local variable, by a finite state machine. The state machine includes multiple states, with transitions among the states, transition conditions associated with the transitions, and procedural blocks, which correspond to the transitions and define operations to be performed on the local variable when traversing the respective transitions. The finite state machine is executed by traversing the transitions in accordance with the respective transition conditions and modifying the local variable in accordance with the respective procedural blocks of the traversed transitions, so as to verify the design with respect to the verification directive.Type: ApplicationFiled: February 27, 2008Publication date: August 27, 2009Inventors: Dmitry Pidan, Sitvanit Ruah