Abstract: Embodiments of the present disclosure includes qubit architectures and qubit elements of a quantum processor. A superconductor region overlaps a three-dimensional topological insulator layer. A vortex region extends through the superconductor region to the three-dimensional topological insulator layer. A peripheral portion of the vortex region is located on an edge of the superconductor region.

Abstract: Quantum devices formed from a single superconducting wire having a configurable ground connection are described. An example quantum device, configurable to be grounded, comprises a single superconducting wire having at least a first section and a second section, each of which is configurable to be in a topological phase and at least a third section configurable to be in a trivial phase. The quantum device further comprises semiconducting regions formed adjacent to the single superconducting wire, where the single superconducting wire is configurable to store quantum information in at least four Majorana zero modes (MZMs). The semiconducting regions formed adjacent to the single superconducting wire may be used to measure quantum information stored in the at least four MZMs.

Abstract: Devices and methods for estimating localization lengths in hybrid superconductor-semiconductor quantum (HSSQ) devices are described. A method for estimating localization lengths in an HSSQ device comprising a set of plunger gates formed in a first layer of the HSSQ device and a set of top gates formed, above the set of plunger gates, in a second layer of the HSSQ device, includes obtaining measurements of nonlocal conductance values associated with the HSSQ device. The at least one junction associated with the HSSQ device attenuates one or more of the measured nonlocal conductance values associated with the HSSQ device. The method further includes normalizing the measured nonlocal conductance values to remove an effect of the attenuation caused by the at least one junction and extracting localization lengths based on the normalized nonlocal conductance values. The method further includes, using a processor, estimating the localization lengths for the HSSQ device.

Abstract: Methods and systems for calibrating a transport gap protocol (TGP) for a device design are described. An example method includes obtaining a non-local conductance threshold by identifying those topological regions of interest (ROIs) for the device design that have an optimized amount of overlap with a topological index associated with the device design. The method further includes thresholding a thermal conductance to obtain both: (1) an estimated topological gap for the device design, and (2) optimal topological ROIs for the device design. The method further includes using a processor, based on the obtained estimated topological gap and the obtained optimal topological ROIs, extracting a topological gap for calibrating the TGP for the device design.

Abstract: Quantum devices formed from a single superconducting wire having a configurable ground connection are described. An example quantum device, configurable to be grounded, comprises a single superconducting wire having at least a first section and a second section, each of which is configurable to be in a topological phase and at least a third section configurable to be in a trivial phase. The quantum device further comprises semiconducting regions formed adjacent to the single superconducting wire, where the single superconducting wire is configurable to store quantum information in at least four Majorana zero modes (MZMs). The semiconducting regions formed adjacent to the single superconducting wire may be used to measure quantum information stored in the at least four MZMs.

Abstract: Methods and systems for estimating localization lengths in hybrid superconductor-semiconductor quantum devices are described. A method for estimating localization lengths in a hybrid superconductor-semiconductor quantum device includes constructing a statistical model for extracting localization lengths based on an implicit description of nonlocal conductance measurements associated with a physical representation of the hybrid superconductor-semiconductor quantum device. The method further includes, using a processor, estimating the localization lengths in the hybrid superconductor-semiconductor quantum device by a joint prior distribution enforcing smoothness over a function of gate voltages and extracted localization lengths for the hybrid superconductor-semiconductor quantum device.

Abstract: Embodiments of the present disclosure includes qubit architectures and qubit elements of a quantum processor. A superconductor region overlaps a three-dimensional topological insulator layer. A vortex region extends through the superconductor region to the three-dimensional topological insulator layer. A peripheral portion of the vortex region is located on an edge of the superconductor region.

Abstract: Examples described in this disclosure relate to gating a semiconductor layer into a quantum spin Hall insulator state, Certain examples further relate to using quantum spin Hall insulators as topological quantum qubits. Quantum spin Hall systems may rely upon the quantum spin Hall effect by causing a state of a matter to change from a certain phase to an inverted bandgap phase. In one example, the present disclosure relates to a device including a semiconductor layer comprising an active material. The device further includes a gate coupled to the semiconductor layer, where the semiconductor layer is operable in a quantum spin Hall insulator state by using electrons and holes from the active material in response to an application of an electric field to the semiconductor layer via the gate.

Abstract: Quantum devices formed from a single superconducting wire having a configurable ground connection are described. An example quantum device, configurable to be grounded, comprises a single superconducting wire having at least a first section and a second section, each of which is configurable to be in a topological phase and at least a third section configurable to be in a trivial phase. The quantum device further comprises semiconducting regions formed adjacent to the single superconducting wire, where the single superconducting wire is configurable to store quantum information in at least four Majorana zero modes (MZMs). The semiconducting regions formed adjacent to the single superconducting wire may be used to measure quantum information stored in the at least four MZMs.

Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes (a) measuring one or both of a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refinement data; (b) finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; and (c) finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

Abstract: A quantum device is fabricated by forming a network of nanowires oriented in a plane of a substrate to produce a Majorana-based topological qubit. The nanowires are formed from combinations of selective-area-grown semiconductor material along with regions of a superconducting material. The selective-area-grown semiconductor material is grown by etching trenches to define the nanowires and depositing the semiconductor material in the trenches. A side gate is formed in an etched trench and situated to control a topological segment of the qubit.

Abstract: Examples described in this disclosure relate to gating a semiconductor layer into a quantum spin Hall insulator state, Certain examples further relate to using quantum spin Hall insulators as topological quantum qubits. Quantum spin Hall systems may rely upon the quantum spin Hall effect by causing a state of a matter to change from a certain phase to an inverted bandgap phase. In one example, the present disclosure relates to a device including a semiconductor layer comprising an active material. The device further includes a gate coupled to the semiconductor layer, where the semiconductor layer is operable in a quantum spin Hall insulator state by using electrons and holes from the active material in response to an application of an electric field to the semiconductor layer via the gate.

Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes (a) measuring one or both of a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction and a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction, to obtain mapping data and refinement data; (b) finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; and (c) finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes measuring a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction to obtain mapping data; finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; measuring a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction in each of the one or more regions of the parameter space, to obtain refinement data; and finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

Abstract: A method to evaluate a semiconductor-superconductor heterojunction for use in a qubit register of a topological quantum computer includes measuring a radio-frequency (RF) junction admittance of the semiconductor-superconductor heterojunction to obtain mapping data; finding by analysis of the mapping data one or more regions of a parameter space consistent with an unbroken topological phase of the semiconductor-superconductor heterojunction; measuring a sub-RF conductance including a non-local conductance of the semiconductor-superconductor heterojunction in each of the one or more regions of the parameter space, to obtain refinement data; and finding by analysis of the refinement data a boundary of the unbroken topological phase in the parameter space and a topological gap of the semiconductor-superconductor heterojunction for at least one of the one or more regions of the parameter space.

Abstract: The disclosure concerns fabricating a quantum device. In an embodiment, a method is disclosed comprising: providing a substrate and an insulator formed on the substrate; from combinations of selective-area-grown semiconductor material along with regions of a superconducting material, forming a network of nanowires oriented in a plane of the substrate which can be used to produce a Majorana-based topological qubit; and fabricating a side gate for controlling a topological segment of the qubit; wherein the selective-area-grown semiconductor material is grown on the substrate, by etching trenches in the insulator formed on the substrate to define the nanowires and depositing the semiconductor material in the trenches defining the nanowires; and wherein the fabricating of the side gate comprises etching the dielectric to create a trench for the side gate and depositing the side gate in the trench for the side gate.