Patents by Inventor Dmitry Vyshetsky
Dmitry Vyshetsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10146279Abstract: A chassis for a storage system contains a digital chamber that houses conventional electronic components and a thermal chamber that houses non-volatile solid state memory such as flash memory. A temperature regulating system monitors temperature within the digital chamber to keep the components therein below their maximum junction temperature. The temperature regulating system tightly regulates the temperature of solid state memory chips to within a nominal operating temperature range selected to extend the lifetime and/or improve the endurance and reliability of the solid state memory. The temperature regulating system may regulate different memory chips to different nominal temperatures based on the operations being performed and lifetime factors for the memory chips including current health and prior use.Type: GrantFiled: March 31, 2016Date of Patent: December 4, 2018Assignee: Western Digital Technologies, Inc.Inventor: Dmitry Vyshetsky
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Patent number: 9594675Abstract: Virtual chip enable techniques perform memory access operations on virtual chip enables rather than physical chip enables. Each virtual chip enable is a construct that includes attributes that correspond to a unique physical or logical memory device.Type: GrantFiled: December 31, 2009Date of Patent: March 14, 2017Assignee: NVIDIA CORPORATIONInventors: Howard Tsai, Dmitry Vyshetsky, Neal Meininger, Paul J. Gyugyi
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Patent number: 9465728Abstract: A memory controller, in one embodiment, includes a command translation data structure, a front end and a back end. The command translation data structure maps command operations to primitives, wherein the primitives are decomposed from command operations determined for one or more memory devices. The front end receives command operations from a processing unit and translates each command operation to a set of one or more corresponding primitives using the command translation data structure. The back end outputs the set of one or more corresponding primitives for each received command operation to a given memory device.Type: GrantFiled: November 3, 2010Date of Patent: October 11, 2016Assignee: NVIDIA CORPORATIONInventors: Howard Tsai, Dmitry Vyshetsky, Neal Meininger
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Publication number: 20160216749Abstract: A chassis for a storage system contains a digital chamber that houses conventional electronic components and a thermal chamber that houses non-volatile solid state memory such as flash memory. A temperature regulating system monitors temperature within the digital chamber to keep the components therein below their maximum junction temperature. The temperature regulating system tightly regulates the temperature of solid state memory chips to within a nominal operating temperature range selected to extend the lifetime and/or improve the endurance and reliability of the solid state memory. The temperature regulating system may regulate different memory chips to different nominal temperatures based on the operations being performed and lifetime factors for the memory chips including current health and prior use.Type: ApplicationFiled: March 31, 2016Publication date: July 28, 2016Inventor: Dmitry VYSHETSKY
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Patent number: 9317083Abstract: A chassis for a storage system contains a digital chamber that houses conventional electronic components and a thermal chamber that houses non-volatile solid state memory such as flash memory. A temperature regulating system monitors temperature within the digital chamber to keep the components therein below their maximum junction temperature. The temperature regulating system tightly regulates the temperature of solid state memory chips to within a nominal operating temperature range selected to extend the lifetime and/or improve the endurance and reliability of the solid state memory. The temperature regulating system may regulate different memory chips to different nominal temperatures based on the operations being performed and lifetime factors for the memory chips including current health and prior use.Type: GrantFiled: February 22, 2013Date of Patent: April 19, 2016Assignee: Skyera, LLCInventor: Dmitry Vyshetsky
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Patent number: 9208108Abstract: A system for selecting a subset of issued flash storage commands to improve processing time for command execution. A plurality of ports stores a first plurality of command identifiers and are associated with the plurality of ports. Each of the first plurality of arbiters selects an oldest command identifier among command identifiers within each corresponding port resulting in a second plurality of command identifiers. A second arbiter makes a plurality of selections from the second plurality of command identifiers based on command identifier age and the priority of the port. A session identifier queue stores commands associated with the plurality of selections among other commands forming a third plurality of commands. A microcontroller selects an executable command from the third plurality of commands for execution based on an execution optimization heuristic. After execution of the command, the command identifier in the port is cleared.Type: GrantFiled: December 19, 2008Date of Patent: December 8, 2015Assignee: NVIDIA CORPORATIONInventors: Dmitry Vyshetsky, Howard Tsai, Paul Gyugyi
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Patent number: 9110714Abstract: In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.Type: GrantFiled: July 16, 2009Date of Patent: August 18, 2015Inventors: Alexander Joffe, Dmitry Vyshetsky
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Publication number: 20140240913Abstract: A chassis for a storage system contains a digital chamber that houses conventional electronic components and a thermal chamber that houses non-volatile solid state memory such as flash memory. A temperature regulating system monitors temperature within the digital chamber to keep the components therein below their maximum junction temperature. The temperature regulating system tightly regulates the temperature of solid state memory chips to within a nominal operating temperature range selected to extend the lifetime and/or improve the endurance and reliability of the solid state memory. The temperature regulating system may regulate different memory chips to different nominal temperatures based on the operations being performed and lifetime factors for the memory chips including current health and prior use.Type: ApplicationFiled: February 22, 2013Publication date: August 28, 2014Applicant: Skyera, Inc.Inventor: Dmitry Vyshetsky
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Patent number: 8694750Abstract: Embodiments of the present invention are directed to a method and system for allowing data structures to be moved between storage locations of varying performance and cost without changing the application firmware. In one embodiment, rather than application firmware directly accessing memory, the application firmware requests a data structure by parameters, to which the implementation returns a pointer. The parameters can be, for example, the logical block address of a data sector, and the data structure can be mapping and associated information of that logical block address (LBA) to a location in the flash device.Type: GrantFiled: December 19, 2008Date of Patent: April 8, 2014Assignee: NVIDIA CorporationInventors: Dmitry Vyshetsky, Paul Gyugyi
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Patent number: 8683293Abstract: An error locator unit for correcting two bit error. The error locator unit includes a plurality of operational units, a normalized basis transform unit, and a conversion unit. The plurality of operations units calculates coefficients of the polynomial based on the generated syndromes in a first basis of a Galois Field. Operating on the coefficients produces a root definition value vector in the first basis. The normalized basis transform unit transforms the root definition value vector to a normal basis to produce a plurality of roots. The conversion unit converts the plurality of roots to the first basis. A scaling factor calculated based on the coefficients is applied to the output of the conversion unit to produce a plurality of scaled roots for said polynomial in the first basis. The plurality of scaled roots is added to produce error locations for the polynomial.Type: GrantFiled: December 16, 2009Date of Patent: March 25, 2014Assignee: Nvidia CorporationInventors: Nirmal Saxena, Howard Tsai, Dmitry Vyshetsky, Paul Gyugyi
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Publication number: 20120110242Abstract: A memory controller, in one embodiment, includes a command translation data structure, a front end and a back end. The command translation data structure maps command operations to primitives, wherein the primitives are decomposed from command operations determined for one or more memory devices. The front end receives command operations from a processing unit and translates each command operation to a set of one or more corresponding primitives using the command translation data structure. The back end outputs the set of one or more corresponding primitives for each received command operation to a given memory device.Type: ApplicationFiled: November 3, 2010Publication date: May 3, 2012Applicant: NVIDIA CORPORATIONInventors: Howard Tsai, Dmitry Vyshetsky, Neal Meininger
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Patent number: 8069355Abstract: A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data path controller can advantageously modify its criteria in-situ so that it can adapt its power management actions in response to changes in processors and peripheral devices. In addition, the data path controller includes a power-managing interface that provides power-monitoring ports for monitoring and/or quantifying power consumption of various components. In one embodiment, the data path controller includes a power-monitoring interface for selectably monitoring power of a component.Type: GrantFiled: December 23, 2008Date of Patent: November 29, 2011Assignee: NVIDIA CorporationInventors: Brad W. Simeral, David G. Reed, Dmitry Vyshetsky, Roman Surgutchik, Robert William Chapman, Joshua Titus, Anand Srinivasan, Hari U. Krishnan
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Publication number: 20110161561Abstract: Virtual chip enable techniques perform memory access operations on virtual chip enables rather than physical chip enables. Each virtual chip enable is a construct that includes attributes that correspond to a unique physical or logical memory device.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Applicant: NVIDIA CORPORATIONInventors: Howard Tsai, Dmitry Vyshetsky, Neal Meininger, Paul J. Gyugyi
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Publication number: 20110161553Abstract: The wear-leveling techniques include discovering a persistent state of one or more memory devices, or building and caching persistent state parameters for each logical unit of a given memory device if a persistent state is not discovered for a given memory device. The techniques may also include processing memory access commands utilizing the cached persistent state parameters. When processing memory access commands, the logical block address and length parameter of a logical address of a command may be translated to a plurality of physical addresses for accessing one or more memory devices, each physical address includes a device address, a logical unit address, a block address, and a page address, wherein the block address includes one or more interleaved address bits.Type: ApplicationFiled: December 30, 2009Publication date: June 30, 2011Applicant: NVIDIA CORPORATIONInventors: Nirmal Saxena, Howard Tsai, Dmitry Vyshetsky, Yen Lin
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Patent number: 7966439Abstract: A system controller includes a memory controller and a host interface residing in different clock domains. There is a time delay between the time when the memory controller issues a read command to a memory and the data becoming present and available at the host interface. The memory controller generates an alarm message at or near the time that it issues the read command. The alarm message indicates to the host interface the time that the data is available for transfer to a host.Type: GrantFiled: November 24, 2004Date of Patent: June 21, 2011Assignee: Nvidia CorporationInventors: Sean J. Treichler, Brad W. Simeral, Roman Surgutchick, Anand Srinivasan, Dmitry Vyshetsky
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Publication number: 20110145677Abstract: An error locator unit for correcting two bit error. The error locator unit includes a plurality of operational units, a normalized basis transform unit, and a conversion unit. The plurality of operations units calculates coefficients of the polynomial based on the generated syndromes in a first basis of a Galois Field. Operating on the coefficients produces a root definition value vector in the first basis. The normalized basis transform unit transforms the root definition value vector to a normal basis to produce a plurality of roots. The conversion unit converts the plurality of roots to the first basis. A scaling factor calculated based on the coefficients is applied to the output of the conversion unit to produce a plurality of scaled roots for said polynomial in the first basis. The plurality of scaled roots is added to produce error locations for the polynomial.Type: ApplicationFiled: December 16, 2009Publication date: June 16, 2011Applicant: NVIDIA CORPORATIONInventors: Nirmal Saxena, Howard Tsai, Dmitry Vyshetsky, Paul Gyugyi
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Publication number: 20100161941Abstract: A system for selecting a subset of issued flash storage commands to improve processing time for command execution. A plurality of ports stores a first plurality of command identifiers and are associated with the plurality of ports. Each of the first plurality of arbiters selects an oldest command identifier among command identifiers within each corresponding port resulting in a second plurality of command identifiers. A second arbiter makes a plurality of selections from the second plurality of command identifiers based on command identifier age and the priority of the port. A session identifier queue stores commands associated with the plurality of selections among other commands forming a third plurality of commands. A microcontroller selects an executable command from the third plurality of commands for execution based on an execution optimization heuristic. After execution of the command, the command identifier in the port is cleared.Type: ApplicationFiled: December 19, 2008Publication date: June 24, 2010Applicant: NVIDIA CorporationInventors: Dmitry Vyshetsky, Howard Tsai, Paul Gyugyi
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Publication number: 20100161876Abstract: Embodiments of the present invention are directed to a method and system for allowing data structures to be moved between storage locations of varying performance and cost without changing the application firmware. In one embodiment, rather than application firmware directly accessing memory, the application firmware requests a data structure by parameters, to which the implementation returns a pointer. The parameters can be, for example, the logical block address of a data sector, and the data structure can be mapping and associated information of that logical block address (LBA) to a location in the flash device.Type: ApplicationFiled: December 19, 2008Publication date: June 24, 2010Applicant: NVIDIA CorporationInventors: Dmitry Vyshetsky, Paul Gyugyi
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Publication number: 20090282408Abstract: In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.Type: ApplicationFiled: July 16, 2009Publication date: November 12, 2009Inventors: Alexander Joffe, Dmitry Vyshetsky
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Patent number: 7590785Abstract: In a multi-tasking pipelined processor, consecutive instructions are executed by different tasks, eliminating the need to purge an instruction execution pipeline of subsequent instructions when a previous instruction cannot be completed. The tasks do not share registers which store task-specific values, thus eliminating the need to save or load registers when a new task is scheduled for execution. If an instruction accesses an unavailable resource, the instruction becomes suspended, allowing other tasks' instructions to be executed instead until the resource becomes available. Task scheduling is performed by hardware; no operating system is needed. Simple techniques are provided to synchronize shared resource access between different tasks.Type: GrantFiled: April 14, 2004Date of Patent: September 15, 2009Assignee: Applied Micro Circuits CorporationInventors: Alexander Joffe, Dmitry Vyshetsky