Abstract: A semiconductor device includes, first and second source/drain patterns on an active pattern and spaced apart from each other, a first source/drain contact on the first source/drain pattern and including a first source/drain barrier film and a first source/drain filling film on the first source/drain barrier film, a second source/drain contact on the second source/drain pattern, and a gate structure on the active pattern between the first and second source/drain contacts and including a gate electrode, wherein a top surface of the first source/drain contact is lower than a top surface of the gate structure, and a height from a top surface of the active pattern to a top surface of the first source/drain barrier film is less than a height from the top surface of the active pattern to a top surface of the first source/drain filling film.

Abstract: A semiconductor device includes, first and second source/drain patterns on an active pattern and spaced apart from each other, a first source/drain contact on the first source/drain pattern and including a first source/drain barrier film and a first source/drain filling film on the first source/drain barrier film, a second source/drain contact on the second source/drain pattern, and a gate structure on the active pattern between the first and second source/drain contacts and including a gate electrode, wherein a top surface of the first source/drain contact is lower than a top surface of the gate structure, and a height from a top surface of the active pattern to a top surface of the first source/drain barrier film is less than a height from the top surface of the active pattern to a top surface of the first source/drain filling film.

Abstract: An integrated circuit device is provided. The integrated circuit device includes a fin-type active region that extends in a first direction on a substrate, a gate structure that intersects with the fin-type active region and extends in a second direction, perpendicular to the first direction, on the substrate, and a first contact structure that is disposed on the gate structure, and has a greater width at a top surface than a bottom surface thereof.

Abstract: An integrated circuit device is provided. The integrated circuit device includes a fin-type active region that extends in a first direction on a substrate, a gate structure that intersects with the fin-type active region and extends in a second direction, perpendicular to the first direction, on the substrate, and a first contact structure that is disposed on the gate structure, and has a greater width at a top surface than a bottom surface thereof.

Abstract: An integrated circuit device is provided. The integrated circuit device includes a fin-type active region that extends in a first direction on a substrate, a gate structure that intersects with the fin-type active region and extends in a second direction, perpendicular to the first direction, on the substrate, and a first contact structure that is disposed on the gate structure, and has a greater width at a top surface than a bottom surface thereof.

Abstract: A semiconductor device includes, first and second source/drain patterns on an active pattern and spaced apart from each other, a first source/drain contact on the first source/drain pattern and including a first source/drain barrier film and a first source/drain filling film on the first source/drain barrier film, a second source/drain contact on the second source/drain pattern, and a gate structure on the active pattern between the first and second source/drain contacts and including a gate electrode, wherein a top surface of the first source/drain contact is lower than a top surface of the gate structure, and a height from a top surface of the active pattern to a top surface of the first source/drain barrier film is less than a height from the top surface of the active pattern to a top surface of the first source/drain filling film.

Abstract: An integrated circuit device is provided. The integrated circuit device includes a fin-type active region that extends in a first direction on a substrate, a gate structure that intersects with the fin-type active region and extends in a second direction, perpendicular to the first direction, on the substrate, and a first contact structure that is disposed on the gate structure, and has a greater width at a top surface than a bottom surface thereof.

Abstract: An integrated circuit device is provided. The integrated circuit device includes a fin-type active region that extends in a first direction on a substrate, a gate structure that intersects with the fin-type active region and extends in a second direction, perpendicular to the first direction, on the substrate, and a first contact structure that is disposed on the gate structure, and has a greater width at a top surface than a bottom surface thereof.

Abstract: An integrated circuit device includes a fin-type active region extending in a first direction parallel on a substrate, a gate structure intersecting with the fin-type active region and extending in a second direction, perpendicular to the first direction, on the substrate, and a first contact structure disposed on the gate structure, an having a greater width at a top surface than a bottom surface thereof.

Abstract: A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.

Abstract: A method of forming patterns of a semiconductor device includes forming a material film on a substrate, forming a hard mask on the material film, forming a first mold mask pattern and a second mold mask pattern on the hard mask, forming a pair of first spacers to cover opposite sidewalls of the first mold mask pattern, and a pair of second spacers to cover opposite sidewalls of the second mold mask pattern, forming a first gap and a second gap to expose the hard mask by removing the first mold mask pattern and the second mold mask pattern, the first gap being formed between the pair of first spacers and the second gap being formed between the pair of second spacers, forming a mask pattern on the hard mask to cover the first gap and expose the second gap, forming an auxiliary pattern to cover the second gap, removing the mask pattern; and forming a hard mask pattern by patterning the hard mask using the first spacers, the second spacers and the auxiliary pattern as a mask.

Abstract: A method of forming patterns of a semiconductor device includes forming a material film on a substrate, forming a hard mask on the material film, forming a first mold mask pattern and a second mold mask pattern on the hard mask, forming a pair of first spacers to cover opposite sidewalls of the first mold mask pattern, and a pair of second spacers to cover opposite sidewalls of the second mold mask pattern, forming a first gap and a second gap to expose the hard mask by removing the first mold mask pattern and the second mold mask pattern, the first gap being formed between the pair of first spacers and the second gap being formed between the pair of second spacers, forming a mask pattern on the hard mask to cover the first gap and expose the second gap, forming an auxiliary pattern to cover the second gap, removing the mask pattern; and forming a hard mask pattern by patterning the hard mask using the first spacers, the second spacers and the auxiliary pattern as a mask.

Abstract: A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.

Abstract: A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.

Abstract: An apparatus and method for processing a substrate using neutralized beams are provided. A substrate processing apparatus includes an ion source generating device configured to form an ion source. An ion extraction device is configured to extract and accelerate ions from the ion source. An ion neutralizing device is configured to convert the ions extracted and accelerated from the ion extraction device into neutralized beams. A remaining portion of the ions extracted and accelerated from the ion extraction device is not converted into the neutralized beams. A substrate support is configured to support a substrate such that the neutralized beams are directed towards the substrate support. A substrate power supply is configured to apply a voltage to the substrate support such that the remaining portion of the ions that is not converted into the neutralized beams is directed away from the substrate support by the applied voltage of the substrate.

Abstract: A semiconductor device is manufactured by a method including processes of trimming and molding resist patterns. A resist layer formed on a substrate is exposed and developed to form the resist patterns. The resist patterns are trimmed using a first gas plasma to change the profiles of the resist patterns. Widths of the trimmed resist patterns are increased using a second gas plasma to form processed resist patterns.

Abstract: A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.

Abstract: An apparatus and method for processing a substrate using neutralized beams are provided. A substrate processing apparatus includes an ion source generating device configured to form an ion source. An ion extraction device is configured to extract and accelerate ions from the ion source. An ion neutralizing device is configured to convert the ions extracted and accelerated from the ion extraction device into neutralized beams. A remaining portion of the ions extracted and accelerated from the ion extraction device is not converted into the neutralized beams. A substrate support is configured to support a substrate such that the neutralized beams are directed towards the substrate support. A substrate power supply is configured to apply a voltage to the substrate support such that the remaining portion of the ions that is not converted into the neutralized beams is directed away from the substrate support by the applied voltage of the substrate.

Abstract: An apparatus and method for processing a substrate using neutralized beams are provided. A substrate processing apparatus includes an ion source generating device configured to form an ion source. An ion extraction device is configured to extract and accelerate ions from the ion source. An ion neutralizing device is configured to convert the ions extracted and accelerated from the ion extraction device into neutralized beams. A remaining portion of the ions extracted and accelerated from the ion extraction device is not converted into the neutralized beams. A substrate support is configured to support a substrate such that the neutralized beams are directed towards the substrate support. A substrate power supply is configured to apply a voltage to the substrate support such that the remaining portion of the ions that is not converted into the neutralized beams is directed away from the substrate support by the applied voltage of the substrate.

Abstract: Disclosed are an atomic layer deposition apparatus using a neutral beam and a method of depositing an atomic layer using the apparatus, capable of converting an ion beam into a neutral beam and radiating it onto a substrate to be treated. The method uses an apparatus for supplying a first reaction gas containing a material that cannot be chemisorbed onto a substrate to be treated into a reaction chamber in which the substrate is loaded, and forming a first reactant adsorption layer containing a material that cannot be chemisorbed onto the substrate; and radiating a neutral beam generated by the second reaction gas onto the substrate on which the first reactant adsorption layer is formed, and removing a material not chemisorbed onto the substrate from the first reactant adsorption layer to form a second reactant adsorption layer.