Abstract: Disclosed herein is a method for integrated anomaly detection. The method includes detecting a thing object and a human object in input video using a first neural network, and tracking the human object, and detecting an anomalous situation based on an object detection result and a human object tracking result.

Abstract: Provided is a positive electrode active material precursor for a rechargeable lithium battery including a nickel-based composite metal hydroxide including a secondary particle in which a plurality of primary particles are agglomerated, wherein the secondary particle includes a central portion and a surface portion, and the surface portion includes a primary particle coated with manganese oxide, manganese hydroxide, or a mixture thereof.

Abstract: A device for performing a refresh operation includes a row control circuit and a row decoder. The row control circuit is configured to generate a bank active signal and a row address for controlling an active operation for a first memory bank based on a refresh signal. The row control circuit is also configured to generate the bank active signal for controlling the active operation for a second memory bank based on a power control signal. The row decoder is configured to receive the bank active signal and the row address to control the active operation for the first memory bank and the second memory bank.

Abstract: A device for performing a refresh operation includes a row control circuit and a row decoder. The row control circuit is configured to generate a bank active signal and a row address for controlling an active operation for a first memory bank based on a refresh signal. The row control circuit is also configured to generate the bank active signal for controlling the active operation for a second memory bank based on a power control signal. The row decoder is configured to receive the bank active signal and the row address to control the active operation for the first memory bank and the second memory bank.

Abstract: A semiconductor memory device includes: first to Nth memory banks each including a normal cell region coupled to normal word lines and a redundant cell region coupled to redundant word lines; first to Nth non-volatile memories that correspond to the first to Nth memory banks, respectively, each including a plurality of memory sets for programming repair addresses of the corresponding memory banks; a refresh control circuit for generating first to Nth count values by counting a number of the memory sets used in the first to Nth non-volatile memories, and generating a redundant reset signal based on the first to Nth count values; and an address generation circuit for sequentially generating normal addresses for selecting the normal word lines and redundant addresses for selecting the redundant word lines based on a refresh signal, and initializing the redundant addresses based on the redundant reset signal.

Abstract: A semiconductor memory device includes: first to Nth memory banks each including a normal cell region coupled to normal word lines and a redundant cell region coupled to redundant word lines; first to Nth non-volatile memories that correspond to the first to Nth memory banks, respectively, each including a plurality of memory sets for programming repair addresses of the corresponding memory banks; a refresh control circuit for generating first to Nth count values by counting a number of the memory sets used in the first to Nth non-volatile memories, and generating a redundant reset signal based on the first to Nth count values; and an address generation circuit for sequentially generating normal addresses for selecting the normal word lines and redundant addresses for selecting the redundant word lines based on a refresh signal, and initializing the redundant addresses based on the redundant reset signal.

Abstract: A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein N is a natural number.

Abstract: A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein N is a natural number.

Abstract: A semiconductor memory apparatus includes a control signal generation unit configured to generate a control signal according to a mode control signal and a refresh signal; a first sense amplifier driving voltage generation unit configured to generate a first sense amplifier driving voltage according to the control signal, a first sense amplifier enable signal and a switching control signal; a switching control unit configured to generate the switching control signal according to the control signal and a second sense amplifier enable signal; a second sense amplifier driving voltage generation unit configured to generate a second sense amplifier driving voltage according to the second sense amplifier enable signal; and a switching unit configured to electrically couple or decouple output nodes of the first sense amplifier driving voltage generation unit and the second sense amplifier driving voltage generation unit according to the switching control signal.