Patents by Inventor Do-Hsing Lee

Do-Hsing Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing semiconductor devices
    Patent number: 8927355
    Abstract: A method of manufacturing a semiconductor device, including the second sacrificial layer receiving a gate structure include a metal and a spacer on a sidewall of the gate structure therethrough being formed on a substrate. The second sacrificial layer is removed. A second etch stop layer and an insulating interlayer are sequentially formed on the gate structure, the spacer and the substrate. An opening passing through the insulating interlayer is formed to expose a portion of the gate structure, a portion of the spacer and a portion of the second etch stop layer on a portion of the substrate. The second etch stop layer being exposed through the opening is removed. The contact being electrically connected to the gate structure and the substrate and filling the opening is formed. The semiconductor device having the metal gate electrode and the shared contact has a desired leakage current characteristic and resistivity characteristics.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: January 6, 2015
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Doo-Young Lee, Ki Il Kim, Myeong-Cheol Kim, Do-Hyoung Kim, Do-Hsing Lee
  • METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES
    Publication number: 20120135577
    Abstract: A method of manufacturing a semiconductor device, including the second sacrificial layer receiving a gate structure include a metal and a spacer on a sidewall of the gate structure therethrough being formed on a substrate. The second sacrificial layer is removed. A second etch stop layer and an insulating interlayer are sequentially formed on the gate structure, the spacer and the substrate. An opening passing through the insulating interlayer is formed to expose a portion of the gate structure, a portion of the spacer and a portion of the second etch stop layer on a portion of the substrate. The second etch stop layer being exposed through the opening is removed. The contact being electrically connected to the gate structure and the substrate and filling the opening is formed. The semiconductor device having the metal gate electrode and the shared contact has a desired leakage current characteristic and resistivity characteristics.
    Type: Application
    Filed: November 28, 2011
    Publication date: May 31, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Doo-Young LEE, Ki Il Kim, Myeong-Cheol Kim, Do-Hyoung Kim, Do-Hsing Lee