Abstract: The present disclosure provides a semiconductor device with a multi-bridge channel field effect transistor. In some embodiments, a semiconductor device includes a substrate, an active pattern that extends in a first horizontal direction on the substrate, a first nanosheet, a second nanosheet, and a gate electrode. The first nanosheet is spaced apart from the active pattern in a vertical direction, and includes a first layer, a second layer disposed on and in contact with the first layer, and a third layer disposed on and in contact with the second layer. The first and third layers include a first material, and the second layer includes a different second material. The second nanosheet is disposed on the first nanosheet and spaced apart from the first nanosheet in the vertical direction. The gate electrode extends in a second horizontal direction on the active pattern and surrounds the first and second nanosheets.

Abstract: A silicon capacitor may include a silicon substrate having a three-dimensional pattern, and a dielectric thin film disposed over the silicon substrate and having a structure with a crystal gradient form. A manufacturing method of a dielectric thin film capacitor may include etching a silicon substrate to form a three-dimensional pattern, depositing an amorphous thin film on the etched silicon substrate at a temperature below 300° C., and embedding crystalline grains in the deposited amorphous thin film by performing plasma treatment. A manufacturing method of a dielectric thin film capacitor may include etching a silicon substrate to form a three-dimensional pattern, depositing an amorphous thin film on the etched silicon substrate at a temperature below 300° C., and depositing a crystalline layer on the deposited amorphous thin film by performing plasma treatment.

Abstract: A semiconductor device includes an active pattern including a lower pattern and a plurality of sheet patterns; a gate structure disposed on the lower pattern and surrounding the plurality of sheet patterns; and a source/drain pattern filling a source/drain recess formed on one side of the gate structure. The source/drain pattern includes a first semiconductor pattern extending along the source/drain recess and contacting the lower pattern, a second and third semiconductor patterns sequentially disposed on the first semiconductor pattern, a lower surface of the third semiconductor pattern is disposed below a lower surface of a lowermost sheet pattern, a side surface of the third semiconductor pattern includes a planar portion, and a thickness of the second semiconductor pattern on the lower surface of the third semiconductor pattern is different from a thickness of the second semiconductor pattern on the planar portion of the side surface of the third semiconductor pattern.