Patents by Inventor Dojun Rhee

Dojun Rhee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6987543
    Abstract: A channel encoding system and a channel decoding system for use in transmitting multiple high definition television programs in a single satellite channel. The channel encoding system may comprise a frame formatter that may be configured to format a transport stream to produce a block stream. An error correction encoder may be configured to encode the block stream to produce an error protected block stream. An interleave module may be configured to interleave the error protected block stream to produce a data stream. A turbo encoder may be configured to encode the data stream to produce an encoded stream. A bit-to-symbol mapper may be configured to map the encoded stream to produce a symbol stream capable of at least eight different symbols. Finally, a modulator may be configured to modulate the symbol stream.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: January 17, 2006
    Assignee: LSI Logic Corporation
    Inventors: Advait M. Mogre, Dojun Rhee
  • Patent number: 6854082
    Abstract: An unequal error protection Reed-Muller code and method for designing a generator matrix and decoder. A conventional RM code is concatenated with the combination of itself and a subcode of itself. The new generator matrix is decomposed to include empty submatrices. The resulting generator matrix allows parallel decoding of separate portions of the received code word vectors.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: February 8, 2005
    Assignee: LSI Logic Corporation
    Inventor: Dojun Rhee
  • Patent number: 6807238
    Abstract: The method of the present invention decodes a received symbol that represents data bits including message bits and parity-check bits. The method comprises (a) mapping the symbol onto a received signal point in a signal space, the signal point having an in-phase component (I) and a quadrature phase component (Q) in the signal space; (b) computing reliability information for each data bit, the reliability information associated with a distance di={square root over ((I−Ii)2+(Q−Qi)2)} between the received signal point (I, Q) and a reference constellation point (Ii, Qi) in the signal space, where i=0, 1, . . .
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: October 19, 2004
    Assignee: LSI Logic Corporation
    Inventors: Dojun Rhee, Advait Mogre
  • Patent number: 6421400
    Abstract: A digital communications receiver is provided with a PSK demodulator and a soft-decision decoder. The PSK demodulator is configured to accept a receive signal and responsively produce quantized baseband signal components which include a quantized radial component RQ and a quantized angular component &thgr;Q. The soft-decision decoder is coupled to the PSK demodulator to receive the quantized baseband signal components and is configured to convert the quantized signal components into decoded information bits. The soft-decision decoder preferably uses a squared Euclidean distance metric calculation for the decoding process. Using polar coordinate quantization provides an improved performance relative to Cartesian coordinate quantization. A new distance metric for TCM decoding is also provided which requires less implementation complexity than a standards Euclidean distance metric calculation, and which suffers no significant performance loss.
    Type: Grant
    Filed: February 4, 1999
    Date of Patent: July 16, 2002
    Assignee: LSI Logic Corporation
    Inventors: Dojun Rhee, Advait Mogre
  • Patent number: 6349117
    Abstract: A recursive decoder for decoding a binary codeword of length N having a first stage, at least one intermediate stage, and a final stage. The first stage including a plurality of decoder groups, each of the groups having a plurality of sets of first and second decoders, each of the first and second decoders having a plurality of inputs and an output, a plurality of adder groups, each of the adders having a first input connected to the output of the first decoder of one of the sets and a second input connected to the output of the second decoder of one of the sets, and an output.
    Type: Grant
    Filed: June 1, 1998
    Date of Patent: February 19, 2002
    Assignee: LSI Logic Corporation
    Inventor: Dojun Rhee
  • Patent number: 6269129
    Abstract: A quadrature amplitude modulation (QAM) trellis coded modulation (TCM) decoder for decoding a stream of QAM TCM signals is disclosed. Each of the signals has a plurality of associated branch metrics and has an in-phase component and a quadrature component. The in-phase component is defined by a plurality of in-phase symbols and the quadrature component is defined by a plurality of quadrature symbols. The QAM TCM decoder includes a first Viterbi decoder and a second Viterbi decoder. The first Viterbi decoder is configured to receive an in-phase component of a QAM TCM signal for decoding the associated in-phase symbols into an in-phase decoded bit and a plurality of uncoded in-phase bits. The second Viterbi decoder configured to receive a quadrature component of the QAM TCM signal for decoding the associated quadrature symbols into a quadrature decoded bit and a plurality of uncoded quadrature bits. The first and second Viterbi decoders are adapted to decode 64- or 256-QAM TCM signals.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: July 31, 2001
    Assignee: LSI Logic Corporation
    Inventors: Dojun Rhee, Chanthachith Souvanthong
  • Patent number: 6233712
    Abstract: An apparatus for recovering information bits from in-phase and quadrature components of a stream of quadrature amplitude modulation (QAM) trellis code modulation (TCM) signals is disclosed. Each signal has an in-phase component and a quadrature component. The in-phase component includes a decoded bit and a plurality of uncoded in-phase bits and the quadrature component includes a decoded quadrature bit and a plurality of uncoded quadrature bits. The apparatus includes a reencode and puncturing circuitry, an inverse mapping circuitry, and a recovery circuitry. The reencode and puncture circuitry is adapted to receive the in-phase and quadrature components of a QAM TCM signal for encoding the decoded in-phase and quadrature bits. The reencode and puncture circuitry punctures the encoded in-phase bit with the uncoded in-phase bits to generate an in-phase component index.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: May 15, 2001
    Assignee: LSI Logic Corporation
    Inventors: Dojun Rhee, Chanthachith Souvanthong
  • Patent number: 6201563
    Abstract: An ATV receiver is provided with a 16-state trellis decoder to achieve improved performance in the presence of NTSC co-channel interference. In one embodiment, the ATV receiver comprises a tuner, a comb filter, and a trellis decoder. The tuner is configured to downmix a selected channel frequency signal to an intermediate frequency signal, where the comb filter is configurable to screen out most of the NTSC co-channel interference. The intermediate frequency receive signal is modified by the comb filter to resemble a partial response signal. The trellis decoder the demodulates the partial response signal in an improved fashion taking into account the state of the trellis encoder and the partial response channel. The trellis decoder may have a 16 state trellis comprised of four 4-state butterflies wherein each edge in the trellis is a single transition.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: March 13, 2001
    Assignee: LSI Logic Corporation
    Inventor: Dojun Rhee
  • Patent number: 5926489
    Abstract: A communications receiver system is presented for detecting burst errors and providing erasure information to a block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, the receiver includes a demodulator which includes circuitry to detect error bursts in the received symbol sequence. Once detected, the locations of symbols in error are marked in the form of erasure flags. An error correction decoder is then able to correct up to twice as many errors with the additional information provided by the erasure flags.
    Type: Grant
    Filed: November 22, 1996
    Date of Patent: July 20, 1999
    Assignee: LSI Logic Corporation
    Inventors: Daniel A. Luthi, Ravi Bhaskaran, Dojun Rhee, Advait M. Mogre
  • Patent number: 5812603
    Abstract: A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: September 22, 1998
    Assignee: LSI Logic Corporation
    Inventors: Daniel A. Luthi, Ravi Bhaskaran, Dojun Rhee, Advait M. Mogre
  • Patent number: 5781569
    Abstract: A differential trellis decoding method for convolutional codes is provided which eliminates from candidacy half of the transitions in each round that it is used, thereby obviating the need for weight calculations for the eliminated transitions. The method is based on a decomposition of the code trellis into fully connected bipartite graphs and the observation that the symmetry of the bipartite graphs of the trellis permits the comparison and selection process for one state to influence the comparison and selection process for other states in the bipartite graph. This method results in a reduced number of operations and hence a reduced complexity for convolutional decoding.
    Type: Grant
    Filed: October 28, 1996
    Date of Patent: July 14, 1998
    Assignee: LSI Logic Corporation
    Inventors: Marc P. C. Fossorier, Shu Lin, Dojun Rhee
  • Patent number: 5708665
    Abstract: A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder (outer decoder), thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.
    Type: Grant
    Filed: August 22, 1996
    Date of Patent: January 13, 1998
    Assignee: LSI Logic Corporation
    Inventors: Daniel A. Luthi, Ravi Bhaskaran, Dojun Rhee, Advait M. Mogre