Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.

Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.

Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.

Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.

Abstract: A memory system includes: a memory device, including a plurality of memory cells, suitable for reading and writing data with a parity bit on a basis of a page; and a memory controller suitable for obtaining an error mask pattern based on compressed data when a number of error bits detected based on the data and the parity bit is equal to or less than a first threshold value and greater than a second threshold value, and controlling to write the compressed data, the parity bit updated based on the compressed data in which the error mask pattern is reflected, compression information on the compressed data and pattern information on the error mask pattern to the page.

Abstract: A semiconductor system may include: a volatile memory device that stores an address mapping table including mapping information for a non-volatile memory device; and a control device suitable for reading one or more seed values from the volatile memory device before the address mapping table is stored, generating a plurality of random values based on the seed values, and initializing mapping information to the plurality of random values.

Abstract: A memory system may include a memory device comprising a plurality of memory banks, and a memory controller suitable for allocating data of successive logical addresses to the respective memory banks, and controlling read/write operations of the data, wherein the memory controller groups pages of the respective memory banks, and performs a wear-leveling operation based on the read/write operations of the data on each group of the pages.

Abstract: A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write accesses for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.

Abstract: A memory controller may include an address control block. The address control block may be configured to remap a write target address when a number of write data having a first logic level is within a correctable range and when a level of a datum corresponding to the write target address has the first logic level.

Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.

Abstract: A memory system may include: a memory device having a plurality of banks, each comprising a memory cell region including a plurality of memory cells, and a page buffer unit; and a controller suitable for receiving a write address and write data from a host, and controlling a write operation of the memory device, wherein the controller comprises: a page buffer table (PBT) comprising fields to retain the same data as the page buffer units of the respective banks; and a processor suitable for comparing the write data to data stored in a field of the PBT, corresponding to the write address, and controlling the memory device to write the write data or the data stored in the page buffer unit to memory cells selected according to the write address, based on a comparison result.

Abstract: A memory system includes a memory device including a plurality of memory blocks, a first detection block suitable for detecting a hot memory block based on a number of times that a write operation is performed among the memory blocks during the write operation, a second detection block suitable for detecting first memory blocks based on the number of times that the write operation is performed among the memory blocks and detecting a cold memory block based on addresses of the first memory blocks, when the hot memory block is detected, and a wear-leveling block suitable for swapping data of the hot memory block for data of the cold memory block.

Abstract: A memory system includes a plurality of memory chips suitable for storing data and an error correction code thereof, an error correction circuit suitable for detecting and correcting error bits of data, which are read from the plurality of memory chips, based on an error correction code of the read data, an address storage circuit suitable for storing addresses of first data, among the read data, the first data having a number of detected error bits greater than or equal to a first number, and a failed chip detection circuit suitable for, when the number of the stored addresses is greater than or equal to a second number, detecting a failed memory chip where a chip-kill occurs by writing test data in the plurality of memory chips and reading back the written test data.

Abstract: A buffer system may include a buffer configured to receive input data having an assigned priority level, store the input data within a memory stack regardless of the priority level assigned to the input data, and sequentially output the input data stored in the memory stack in order of the priority levels assigned to the input data.

Abstract: A memory system may include a nonvolatile memory device and a wear leveling unit. The nonvolatile memory device includes a plurality of memory blocks. The wear leveling unit may be configured to intermittently increase an accumulative access count of a memory block among the memory blocks by a predetermined value, decide a wear level of the memory block based on the accumulative access count whenever the accumulative access count is increased, set the memory block to a hot block based on the wear level, and perform a hot block management operation on the hot block. The wear leveling unit may increase the accumulative access count in response to an access count reaching a predetermined value. The accumulative access count may be stored in the nonvolatile memory device, and the access count may be stored in a volatile memory device.

Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.

Abstract: A memory device includes a memory region; and an access unit suitable for setting an offset value according to control of an external device, changing, in response to an access command of the external device for a first address of the memory region, the first address into a second address of the memory region based on the offset value, and performing an access operation for the second address.

Abstract: A memory module includes a first memory device that includes first circuit nodes for communication with a memory controller and second circuit nodes for communication inside the memory module, a second memory device that includes first circuit nodes for communication with the memory controller and second circuit nodes for communication inside the memory module, and an internal data bus that couples the first memory device to the second memory device to carry data between the second circuit nodes of the first memory device and the second circuit nodes of the second memory device. When an internal read command is applied to the first memory device and an internal write command is applied to the second memory device, data is transferred from the first memory device to the second memory device through the internal data bus.

Abstract: A memory system includes a memory device including one or more memory blocks, and configured to store data in a plurality of pages included in each memory block through a write operation, and a memory controller configured to count an operation number of write operations performed on the memory block, check whether the write operation is performed for each of the pages, select one or more victim pages among the pages, and copy data stored in the victim pages.

Abstract: A semiconductor system may include a memory device and a controller. The memory device may include a plurality of decks. Each of the decks may include word lines and bit lines alternately stacked. The controller may control an operation for data of the decks included in the memory device. The controller may include a counting circuit block for counting access numbers of the word lines and the bit lines. The counting circuit block may include a plurality of x-counting blocks corresponding to the word lines that are stacked a plurality of y-counting blocks corresponding to the bit lines that are stacked. The x-counting blocks may count access numbers of selected word lines in accordance with a selection signal of a corresponding deck among the decks. The y-counting block may count access numbers of selected bit lines in accordance with the selection signal of the corresponding deck.