Abstract: A semiconductor device includes: transistors stacked in a vertical direction; a bit line electrically connected to a first end of each of the transistors; and a data storage structure electrically connected to a second end of each of the transistors. The data storage structure includes: conductive pillars extending in a first horizontal direction; an electrode pattern covering the conductive pillars; and a dielectric layer between each of the conductive pillars and the electrode pattern. The first horizontal direction is perpendicular to the vertical direction and is a direction oriented from the bit line to the data storage structure, each of the conductive pillars has a first side surface adjacent to a corresponding transistor among the transistors, and a second side surface opposite to the first side surface, and the second side surface of a first conductive pillar among the conductive pillars has a convex shape.

Abstract: A semiconductor device including a substrate, a plurality of semiconductor patterns on the substrate, a bit line contacting a first end portion of each semiconductor pattern in a first direction and extending in a third direction perpendicular to an upper surface of the substrate, a plurality of word lines overlapping the plurality of semiconductor patterns, respectively, in the third direction and extending in a second direction intersecting the first direction, and a plurality of capacitors contacting a second end portion of each semiconductor pattern along the first direction. Each word line includes a first conductive liner layer, a second conductive liner layer, and a conductive layer sequentially positioned on each semiconductor pattern. The first conductive liner layer and the second conductive liner layer include different materials from each other or include same materials having different composition ratios from each other.

Abstract: A semiconductor device includes channels extending in a first horizontal direction and spaced apart from each other in a second horizontal direction intersecting the first horizontal direction; a bit line extending in a vertical direction and contacting first ends of the channels; a gate electrode extending in the second horizontal direction and surrounding each of the channels; gate dielectric layers each arranged between the gate electrode and a respective channel of the channels; a mold surrounding the gate electrode; a metal growth suppression layer arranged between the gate electrode and the mold; and a data storage extending in the vertical direction and contacting second ends of the channels opposite the first ends of the channels.

Abstract: A semiconductor device including a bit line extending in a vertical direction on a substrate, a transistor body electrically connected to the bit line and including a first source/drain region, a channel region, and a second source/drain region in a first horizontal direction, a gate electrode extending in a second horizontal direction intersecting the first horizontal direction and on the channel region where a gate dielectric layer is between the gate electrode and the channel region, and a cell capacitor electrically connected to the second source/drain region and including a storage electrode, a capacitor dielectric layer and a plate electrode in the first horizontal direction. A doped polysilicon layer and a contact metal layer are both between the second source/drain region and the storage electrode.

Abstract: A semiconductor memory device includes: a back gate electrode, which includes a first conductive pattern, on a substrate; a first gate electrode, which includes a second conductive pattern, on the back gate electrode; and a first semiconductor pattern between the back gate electrode and the first gate electrode, wherein the first conductive pattern and the second conductive pattern include respective materials and/or have respective physical properties different from each other.

Abstract: A semiconductor device may include a bit line extending in a first direction, a first semiconductor vertical portion on the bit line and extending in a vertical direction, a first word line adjacent to the first semiconductor vertical portion, a gate insulating pattern between the first semiconductor vertical portion and the first word line, and a contact pattern on an upper surface of the first semiconductor vertical portion. The vertical direction may be perpendicular to an uppermost surface of the bit line. The upper surface of the first semiconductor vertical portion may be positioned at a lower height than an upper surface of the first word line and an upper surface of the gate insulating pattern. The contact pattern may include metal. A grain size of the metal may be greater than 10 nm and less than 40 nm.

Abstract: A semiconductor device includes a first structure including a first insulating layer and a first conductive wiring arranged on the first insulating layer, a second-1 insulating layer arranged above the first structure in a first direction, a via hole penetrating the second-1 insulating layer in the first direction, a barrier layer arranged at a lower side of the via hole, and a via plug electrically connected to the first conductive wiring and arranged to fill a remaining space in an internal space of the via hole, excluding the barrier layer.

Abstract: A semiconductor device includes a substrate, an active pattern extending in a first direction on the substrate, a gate electrode extending in a second direction that intersects with the first direction on the substrate, a source/drain pattern on the active pattern, a contact plug spaced apart from the gate electrode in the first direction, an insulating layer on the gate electrode and the contact plug, a first metal layer on the gate electrode in a first hole extending through the insulating layer in a third direction that intersects with the first direction and the second direction, a second metal layer on the contact plug in a second hole extending through the insulating layer in the third direction, a first metal wire on the first metal layer and the insulating layer, and a second metal wire on the second metal layer and the insulating layer.

Abstract: An interconnection structure may include a first insulating interlayer on a substrate, a first metal pattern on the substrate and passing through the first insulating interlayer, a seed metal layer pattern surrounding a portion of a sidewall of the first metal pattern and a bottom of the first metal pattern, and a second metal pattern. The second metal pattern may directly contact an uppermost surface of the seed metal layer pattern, the upper sidewall of the first metal pattern, and the upper surface of the first metal pattern. An upper sidewall and an upper surface of the first metal pattern may be exposed by the seed metal layer pattern. The second metal pattern may fill at least a recess between the first insulating interlayer and the first metal pattern.

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

Abstract: A microelectronic device includes a substrate having at least one microelectronic component on a surface thereof, a conductive via electrode extending through the substrate, and a stress relief structure including a gap region therein extending into the surface of the substrate between the via electrode and the microelectronic component. The stress relief structure is spaced apart from the conductive via such that a portion of the substrate extends therebetween. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device may include a semiconductor substrate, a through via electrode, and a buffer. The through via electrode may extend through a thickness of the semiconductor substrate with the through via electrode surrounding an inner portion of the semiconductor substrate so that the inner portion of the semiconductor substrate may thus be isolated from the outer portion of the semiconductor substrate. The buffer may be in the inner portion of the semiconductor substrate with the through via electrode surrounding and spaced apart from the buffer. Related methods are also discussed.

Abstract: A semiconductor device having a chip stack and an interconnection terminal is provided. The chip stack includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on each other. The interconnection terminal is electrically coupled to the chip stack. The first semiconductor chip includes a first front surface and a first backside surface. The second semiconductor chip includes a second front surface, a second backside surface, a second circuit layer and a through-electrode which is electrically coupled to the second circuit layer and penetrates the second semiconductor chip. The third semiconductor chip includes a third front surface, a third backside surface opposite to the third front surface and a third circuit layer adjacent to the third front surface. The first front surface and the second front surface face each other. The third front surface and the second backside surface face each other.

Abstract: Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode.

Abstract: Provided are semiconductor devices having through electrodes and methods of fabricating the same. The method includes providing a substrate including top and bottom surfaces facing each other, forming a hole and a gap extending from the top surface of the substrate toward the bottom surface of the substrate, the gap surrounding the hole and being shallower than the hole, filling the hole with an insulating material, forming a metal interconnection line on the top surface of the substrate on the insulating material, recessing the bottom surface of the substrate to expose the insulating material, removing the insulating material to expose the metal interconnection line via the hole, filling the hole with a conductive material to form a through electrode connected to the metal interconnection line, recessing the bottom surface of the substrate again to expose the gap, and forming a lower insulating layer on the bottom surface of the substrate.

Abstract: Provided are a semiconductor chip and a method of manufacturing the same. The semiconductor chip includes a substrate having a first side and a second side facing each other, and a through electrode being disposed in a hole penetrating the substrate, wherein an opening surrounded by the through electrode is disposed in the hole, wherein the opening comprises a first end adjacent to the first side of the substrate and a second end adjacent to the second side of the substrate.

Abstract: Provided are semiconductor devices having through electrodes and methods of fabricating the same. The method includes providing a substrate including top and bottom surfaces facing each other, forming a hole and a gap extending from the top surface of the substrate toward the bottom surface of the substrate, the gap surrounding the hole and being shallower than the hole, filling the hole with an insulating material, forming a metal interconnection line on the top surface of the substrate on the insulating material, recessing the bottom surface of the substrate to expose the insulating material, removing the insulating material to expose the metal interconnection line via the hole, filling the hole with a conductive material to form a through electrode connected to the metal interconnection line, recessing the bottom surface of the substrate again to expose the gap, and forming a lower insulating layer on the bottom surface of the substrate.

Abstract: Provided are a semiconductor chip and a method of manufacturing the same.

Abstract: Provided are semiconductor devices having through electrodes and methods of fabricating the same. The method includes providing a substrate including top and bottom surfaces facing each other, forming a hole and a gap extending from the top surface of the substrate toward the bottom surface of the substrate, the gap surrounding the hole and being shallower than the hole, filling the hole with an insulating material, forming a metal interconnection line on the top surface of the substrate on the insulating material, recessing the bottom surface of the substrate to expose the insulating material, removing the insulating material to expose the metal interconnection line via the hole, filling the hole with a conductive material to form a through electrode connected to the metal interconnection line, recessing the bottom surface of the substrate again to expose the gap, and forming a lower insulating layer on the bottom surface of the substrate.