Abstract: A semiconductor device includes an active pattern. A first source or drain region and a second source or drain region are formed at upper portions of the active pattern. The first source or drain region and the second source or drain region are each disposed adjacent to the gate structure. The gate structure is disposed between the first source or drain region and the second source or drain region. A conductive line is electrically connected to the first source or drain region, the conductive line including a first portion and a second portion. A width of the first portion is greater than a width of the second portion. The width of the first and second portions of the conductive line is measured along a first direction in plan view. A conductive contact is electrically connected to the second source or drain region.

Abstract: A method of manufacturing a semiconductor device includes forming an isolation pattern on a substrate to define active patterns each having a first contact region at a center portion thereof and second and third contact regions at edge portions thereof. The method further includes forming a buried gate structure at upper portions of the isolation pattern and the active patterns, forming a first insulation layer on the isolation pattern and the active patterns, and etching a portion of the first insulation layer and an upper portion of the first contact region to form a preliminary opening exposing the first contact region. The method still further includes etching the isolation pattern to form an opening, forming an insulation pattern on a sidewall of the opening, and forming a wiring structure contacting the first contact region in the opening.

Abstract: A method of manufacturing a semiconductor device includes forming an isolation pattern on a substrate to define active patterns each having a first contact region at a center portion thereof and second and third contact regions at edge portions thereof. The method further includes forming a buried gate structure at upper portions of the isolation pattern and the active patterns, forming a first insulation layer on the isolation pattern and the active patterns, and etching a portion of the first insulation layer and an upper portion of the first contact region to form a preliminary opening exposing the first contact region. The method still further includes etching the isolation pattern to form an opening, forming an insulation pattern on a sidewall of the opening, and forming a wiring structure contacting the first contact region in the opening.