Abstract: A method of calculating a collision risk of a ship according to an embodiment of the present disclosure may include: calculating an available velocity area based on maneuvering performance of a host ship; calculating a velocity obstacle area where there is a possibility of collision between an object and the host ship; and calculating a collision risk based on at least one of the available velocity area, the velocity obstacle area, and a preset weight.

Abstract: An apparatus for treating a substrate includes a body having an inner space in which the substrate is dried by a drying fluid in a supercritical state, a fluid supply unit that supplies the drying fluid into the inner space, a fluid exhaust unit that releases the drying fluid from the inner space, and a controller. The controller controls the fluid supply unit and the fluid exhaust unit to perform a pressure-raising step of raising pressure in the inner space to a set pressure and a flow step of generating a flow of the drying gas in the inner space by releasing, by the fluid exhaust unit, the drying fluid from the inner space while the fluid supply unit supplies the drying fluid into the inner space.

Abstract: Disclosed herein are an apparatus and method for calculating a multiplicative inverse. The apparatus for calculating a multiplicative inverse includes a data input unit for receiving input data, a multiplicative inverse calculation unit for dividing an input degree-8 finite field corresponding to the input data into two first degree-4 finite fields so as to perform Advanced Encryption Standard (AES) encryption on the input data, and for performing a multiplicative inverse calculation on the first degree-4 finite fields in consideration of a circuit depth value (T-Depth) and qubit consumption of quantum gates in a quantum circuit, and a data output unit for outputting result data obtained by performing the multiplicative inverse calculation.

Abstract: A method of manufacturing a semiconductor device, the method including providing a substrate including a first region and a second region such that the second region is separated from the first region; forming a metal oxide film on the first region of the substrate and the second region of the substrate; forming an upper metal material film on the metal oxide film on the first region of the substrate such that the upper metal material film does not overlap the metal oxide film on the second region of the substrate; and simultaneously annealing the upper metal material film and the metal oxide film to form a ferroelectric insulating film on the first region of the substrate and form a paraelectric insulating film on the second region of the substrate.

Abstract: A semiconductor device includes a substrate, a first active pattern disposed on the substrate, a second active pattern stacked on the first active pattern, a first gate structure extending to intersect the first active pattern and the second active pattern, a second gate structure spaced apart from the first gate structure and extending to intersect the first active pattern and the second active pattern, a first epitaxial pattern interposed between the first gate structure and the second gate structure, and connected to the first active pattern, a second epitaxial pattern interposed between the first gate structure and the second gate structure, and connected to the second active pattern, an insulating pattern interposed between the first epitaxial pattern and the second epitaxial pattern, and a semiconductor film interposed between the insulating pattern and the second epitaxial pattern, the semiconductor film extending along a top surface of the insulating pattern.

Abstract: A semiconductor device includes an active pattern on a substrate extending in a first horizontal direction, a gate electrode on the active pattern extending in a second horizontal direction, a source/drain region on the active pattern, an upper source/drain region apart from the lower source/drain region, a lower source/drain between upper and lower source/drain regions and connected to the lower source/drain region, an upper source/drain connected to an upper source/drain region, an interlayer insulating layer surrounding the upper source/drain region, a through-via on opposing sidewalls in the second horizontal direction extending through the interlayer insulating layer in the vertical direction, the through-via being spaced from the upper source/drain region and upper source/drain contact in the second horizontal direction, the through-via being connected to the lower source/drain contact, and a dam structure on each of the opposing sidewalls in the horizontal direction of the upper source/drain region.

Abstract: A semiconductor device includes a substrate, an active pattern on the substrate, a plurality of lower nanosheets stacked on the active pattern, a separation structure spaced apart from the plurality of lower nanosheets in the vertical direction and disposed on the plurality of lower nanosheets, and including first to third layers sequentially stacked on each other, a plurality of upper nanosheets spaced apart from the separation structure in the vertical direction and disposed on the separation structure, and stacked on the separation structure, and a gate electrode extending in a second horizontal direction different from the first horizontal direction, and surrounding the separation structure, each of the plurality of lower nanosheets, and each of the plurality of upper nanosheets. The first and third layers include the same material, and each of the first layer and the third layer includes a material different from a material of the second layer.

Abstract: A semiconductor device including a lower pattern extending in a first direction, a gate electrode on the lower pattern and extending in a second direction, a lower channel pattern on the lower pattern and comprising at least one lower sheet pattern, an upper channel pattern on the lower channel pattern and comprising at least one upper sheet pattern, wherein the upper channel pattern is spaced apart from the lower channel pattern in a third direction, the gate electrode comprises a lower gate electrode through which the lower sheet pattern passes and an upper gate electrode through which the upper sheet pattern passes, the lower gate electrode comprises a lower conductive liner layer defining a trench and a lower filling layer filling the trench, and an entire bottom surface of the upper gate electrode is higher than an upper surface of the lower gate electrode, may be provided.

Abstract: HTS screening was performed regarding cell proliferation, one of symptoms of senescence. As a result, KB1541, which was the most effective on cell proliferation, was earned. The present invention described how the compound regulates cell proliferation and senescence. The present invention uncovered what proteins interacted with the compound using streptavidin-magnetic beads after treating with biotin-connected KB1541. Consequently, it was identified that mitochondrial proteins interacted with the compound. In ATP assay, electron microscope and IP assay, the inventors identified that the compound regulated mitochondrial proteins and thereby increased ATP production as well as recovered senescence.

Abstract: A camera module according to the present invention may comprise: a barrel that accommodates a lens therein; a printed circuit board formed under the barrel and mounted with an image sensor; a body portion integrally formed with the barrel; a holder comprising a leg portion formed by being extended downward from the lower end of the body portion to the same height as the image plane of the lens; and a fixing portion formed downward from the leg portion to have a predetermined thickness to fix the holder to the printed circuit board, wherein the thickness of the fixing portion may be equal to the height from the upper surface of the printed circuit board to the image plane of the image sensor.

Abstract: A semiconductor device comprises a substrate, a first active pattern on the substrate and extending in a first direction, a second active pattern extending in the first direction spaced apart from the substrate, a gate electrode extending in a second direction surrounding the first and second active patterns, and a high dielectric film between the first and second active patterns and the gate electrode. The gate electrode includes first and second work function adjusting films surrounding the high dielectric film on the first and second active patterns, and a filling conductive film surrounding the first and second work function adjusting films. The first and second work function adjusting films include first and second work function conductive films, each of which includes a first metal film. A thickness of the first metal film of the first work function conductive film is greater than that of the second work function conductive film.

Abstract: A semiconductor memory device and a method for manufacturing the same. The semiconductor memory device may include a substrate, a first lower wire pattern and a first upper wire pattern stacked on the substrate, and spaced apart from each other; a second lower wire pattern and a second upper wire pattern stacked on the substrate, spaced apart from each other, and spaced apart from the first lower and upper wire patterns; a first gate line surrounding the first lower wire pattern and the first upper wire pattern; a second gate line surrounding the second lower wire pattern and the second upper wire pattern and spaced apart from the first gate line; a first lower source/drain area; a first upper source/drain area; and a first overlapping contact that electrically connects the first lower source/drain area, the first upper source/drain area and the second gate line to each other.

Abstract: A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern.

Abstract: A method of manufacturing a semiconductor device, the method including providing a substrate including a first region and a second region such that the second region is separated from the first region; forming a metal oxide film on the first region of the substrate and the second region of the substrate; forming an upper metal material film on the metal oxide film on the first region of the substrate such that the upper metal material film does not overlap the metal oxide film on the second region of the substrate; and simultaneously annealing the upper metal material film and the metal oxide film to form a ferroelectric insulating film on the first region of the substrate and form a paraelectric insulating film on the second region of the substrate.

Abstract: Provided is a semiconductor device. The semiconductor device comprises a first active pattern extending in a first direction on a substrate, a second active pattern which extends in the first direction and is adjacent to the first active pattern in a second direction different from the first direction, a field insulating film placed between the first active pattern and the second active pattern, a first gate structure which crosses the first active pattern, extends in the second direction, and includes a first gate electrode and a first gate spacer, a second gate structure which crosses the second active pattern, extends in the second direction, and includes a second gate electrode and a second gate spacer, a gate separation structure placed on the field insulating film between the first gate structure and the second gate structure.

Abstract: A camera module according to the present invention may comprise: a barrel that accommodates a lens therein; a printed circuit board formed under the barrel and mounted with an image sensor; a body portion integrally formed with the barrel; a holder comprising a leg portion formed by being extended downward from the lower end of the body portion to the same height as the image plane of the lens; and a fixing portion formed downward from the leg portion to have a predetermined thickness to fix the holder to the printed circuit board, wherein the thickness of the fixing portion may be equal to the height from the upper surface of the printed circuit board to the image plane of the image sensor.

Abstract: In some embodiments, a composition for the treatment and inhibition or prevention of arthritic diseases includes an extract of mixed herbs, the mixed herbs including an active ingredient with Lonicera japonica THUNB and Anemarrhena asphodeloides BUNGE.

Abstract: The present invention is directed to an ultrasound system and a method for reformatting a planar image. The ultrasound system includes a volume data acquiring unit and an image processing unit. The volume data acquiring unit may acquire volume data by transmitting/receiving ultrasound signals to/from a target object of an un-echoic area. The image processing unit may perform inverse volume rendering upon the volume data to form a 3-dimensional image showing the target object and set a region of interest (ROI) on the target object in response to a user input. The image processor detects data corresponding to the ROI from the volume data and reformats the detected data to form a planar image.

Abstract: In some embodiments, a composition for the treatment and inhibition or prevention of arthritic diseases includes an extract of mixed herbs, the mixed herbs including an active ingredient with Lonicera japonica THUNB and Anemarrhena asphodeloides BUNGE.

Abstract: There is provided an image processing system, which includes: a volume data processor for forming volume data based on image signals and setting at least one frame in the volume data; an AGC/LGC parameter setting unit for setting axial gain compensation (AGC) and lateral gain compensation (LGC) parameters based on the frame; a gain parameter setting unit for setting a gain parameter based on the frame; an amplifying unit for performing AGC/LGC upon image signals based on the AGC/LGC parameters and amplifying the image signals based on the gain parameter; a brightness adjusting unit for analyzing intensities of pixels included in the volume data formed based on the image signal performing the AGC/LGC and adjusting the gain, and adjusting brightness of the volume data based on the analysis result; and an image processor for forming images based on the frame and the volume data.