Patents by Inventor Doddaballapur N. Jayasimha

Doddaballapur N. Jayasimha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130051391
    Abstract: A method for routing information in a flexible routing network which connects disparate initiators and targets includes implementing a packetization logic at an interface between an initiator or a target and a routing network to receive transmission traffic from the initiator or the target and to packetize the transmission traffic into packets. Each packet includes a header portion and a body portion. Each of the header portion and the body portion includes one or more standard sized transmission units. Each standard sized transmission unit includes a control section and a payload section. A payload section associated with the body portion includes one or more chunks. The method includes encoding the one or more chunks using the CDF. All transmissions within the routing network are based on the CDF. The CDF facilitates narrow-to-wide and wide-to-narrow link width conversion without having to manipulate subparts of data fields in the transmission traffic.
    Type: Application
    Filed: August 26, 2011
    Publication date: February 28, 2013
    Applicant: SONICS, INC.
    Inventors: Doddaballapur N. Jayasimha, Jeremy Chan, Jay S. Tomlinson
  • Publication number: 20130051397
    Abstract: A method includes receiving flits forwarded from an upstream router into a first input virtual channel (VC) associated with an input port. The flits are associated with packets originated from a first Intellectual Property (IP) core and forwarded to a second IP core. The flits are stored in a VC storage associated with the first input VC. The method further includes performing link width conversion based on a width of the flits being different from a width of an output port. Link width conversion includes accumulation of the flits when the width of the output port is wider and unpacking of the flits when the width of the output port is narrower. Credits are generated based on the flits being forwarded from the first input VC to the output port. The credits are sent to the upstream router to enable receiving more flits from the upstream router.
    Type: Application
    Filed: August 26, 2011
    Publication date: February 28, 2013
    Applicant: SONICS, INC.
    Inventors: LIPING GUO, DODDABALLAPUR N. JAYASIMHA, JEREMY CHAN
  • Publication number: 20110213949
    Abstract: Various methods and apparatus are described for communicating transactions between one or more initiator IP cores and one or more target IP cores coupled to an interconnect. Tag logic may be located within the interconnect, such as located in an agent, and configured to assign different interconnect tag identification numbers to two or more transactions from a same thread. The tag logic assigns different interconnect tag identification numbers to allow the two or more transactions from the same thread to be outstanding over the interconnect to two or more different target IP cores at the same time, allow the two or more transactions from the same thread to be processed in parallel over the interconnect, and potentially serviced out of issue order while being returned back to the multiple threaded initiator IP core realigned in expected execution order.
    Type: Application
    Filed: March 1, 2010
    Publication date: September 1, 2011
    Applicant: SONICS, INC.
    Inventors: Doddaballapur N. Jayasimha, Luc Hoa Ton, Drew E. Wingard
  • Patent number: 7738484
    Abstract: Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. For example, the POC values could be from the following: Platform Input Clock to Core Clock Ratio, Enable/disable LT, Configurable Restart, Burn In Initialization Mode, Disable Hyper Threading, System BSP Socket Indication, and Platform Topology Index.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: June 15, 2010
    Assignee: Intel Corporation
    Inventors: Mani Ayyar, Srinivas Chennupaty, Akhilesh Kumar, Doddaballapur N. Jayasimha, Murugasamy Nachimuthu, Phanindra K. Mannava
  • Publication number: 20090274157
    Abstract: A method and apparatus for hierarchical routing in mesh systems. The method may include splitting 420 a mesh network of nodes into a plurality of partitions, each partition including at least one node, dividing 430 a first partition into a plurality of rectangular regions, determining 440 a partition route from a source region to a destination region of the plurality of rectangular regions, and providing 450 a region route from a source node within one of the plurality of rectangular regions to a destination node within the same rectangular region. The method may also include routing 460 a packet from a source node within the source region to a destination node within the destination region using the partition route and the region route.
    Type: Application
    Filed: May 1, 2008
    Publication date: November 5, 2009
    Inventors: Aniruddha S. Vaidya, Doddaballapur N. Jayasimha
  • Patent number: 7328368
    Abstract: In some embodiments an apparatus includes a transmission error detector to detect an error of a transmission of an interconnect and a transmitting agent to retry the transmission in response to the detected error. The apparatus also includes a hard failure detector to detect a hard failure of the interconnect if the retry is unsuccessful, and a transmission width reducer to reduce a transmission width of the interconnect in response to the hard failure detector. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 12, 2004
    Date of Patent: February 5, 2008
    Assignee: Intel Corporation
    Inventors: Phanindra K. Mannava, Victor W. Lee, Akhilesh Kumar, Doddaballapur N. Jayasimha, Ioannis T. Schoinas
  • Patent number: 6704845
    Abstract: A snoop filter in a multi-processor system maintains a plurality of entries, each representing a cache line that may be owned by one or more nodes. When replacement of one of the entries is required, the snoop filter selects for replacement the entry representing the cache line or lines owned by the fewest nodes, as determined from a presence vector in each of the entries. A temporal or other type of algorithm is used to refine the selection if more than one cache line is owned by the fewest number of nodes.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: March 9, 2004
    Assignee: Intel Corporation
    Inventors: James R. Anderson, Doddaballapur N. Jayasimha
  • Publication number: 20030177317
    Abstract: A snoop filter in a multi-processor system maintains a plurality of entries, each representing a cache line that may be owned by one or more nodes. When replacement of one of the entries is required, the snoop filter selects for replacement the entry representing the cache line or lines owned by the fewest nodes, as determined from a presence vector in each of the entries. A temporal or other type of algorithm is used to refine the selection if more than one cache line is owned by the fewest number of nodes.
    Type: Application
    Filed: April 14, 2003
    Publication date: September 18, 2003
    Applicant: Intel Corporation
    Inventors: James R. Anderson, Doddaballapur N. Jayasimha
  • Patent number: 6598123
    Abstract: A snoop filter in a multi-processor system maintains a plurality of entries, each representing a cache line that may be owned by one or more nodes. When replacement of one of the entries is required, the snoop filter selects for replacement the entry representing the cache line or lines owned by the fewest nodes, as determined from a presence vector in each of the entries. A temporal or other type of algorithm is used to refine the selection if more than one cache line is owned by the fewest number of nodes.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: July 22, 2003
    Assignee: Intel Corporation
    Inventors: James R. Anderson, Doddaballapur N. Jayasimha