Abstract: Provided is concerned with a high voltage switch circuit for a semiconductor device, which rapidly discharges a gate voltage of a pass transistor through an additional discharge transistor during inactivation of itself in the circuit structure with a positive feedback loop for transferring an internal high voltage without a voltage drop by applying an enough voltage to the gate of the pass transistor. The high voltage switch circuit prevents the internal high voltage from decreasing.

Abstract: The present invention discloses a high voltage switch circuit of a semiconductor device which can efficiently switch a high voltage over about 20V required in a flash memory even in a low voltage below about 1.4V by reducing increase of a threshold voltage by a back bias, facilitate development of a low voltage memory device, and reduce an area of a pumping capacitor.

Abstract: Provided is a method of measuring threshold voltages in a NAND flash memory device. In the method, a test voltage is applied to a wordline of selected memory cells to measure a distribution profile of threshold voltages of memory cells. A voltage summing up a pass voltage and an operation voltage is applied to wordlines of deselected cells. The operation voltage is applied to a well and a common source line. A voltage summing up a precharge voltage and the operation voltage is applied to a bitline. After then, a voltage variation on the bitline can be detected to measure a threshold voltage of a memory cell. A negative threshold voltage can be measured by applying a positive voltage with reference to a voltage, as the threshold voltage of the memory cell, set by subtracting the operation voltage from the test voltage in accordance with the bitline voltage variation.

Abstract: A page buffer for an NAND flash memory, including: a first latch for loading data; a second latch for storing data stored on a cell depending on a bit line selection signal; a setting circuit for setting the first latch to a high level to load data in a high level; a first switching circuit for transferring the data stored on the second latch depending on a data output signal of a page buffer; a discharging circuit for discharging charges on a data line; a second switching circuit for connecting the data line discharged by the discharging circuit to the first latch depending on a data control signal to load the data in a low level to the first latch; and a data transferring circuit for transferring the data of the first latch to the second latch.

Abstract: The present invention provides a page buffer for an NAND flash memory, comprising: a first latch for loading data; a second latch for storing data stored on a cell depending on a bit line selection signal; a setting mean for setting the first latch to a high level to load data in a high level; a first switching mean for transferring the data stored on the second latch depending on a data output signal of a page buffer; a discharging mean for discharging charges on a data line; a second switching mean for connecting the data line discharged by the discharging mean to the first latch depending on a data control signal to load the data in a low level to the first latch; and a data transferring mean for transferring the data of the first latch to the second latch.

Abstract: An address transition signal detecting circuit includes a differentiator for receiving and differentiating an address input signal, and a pulse signal forming portion for receiving the signal differentiated in the differentiator to thereby form an address transition signal.