Abstract: A memory module includes a first memory device including a first plurality of memory banks, a second plurality of memory banks, and a first refresh management circuit, and a second memory device including a third plurality of memory banks, a fourth plurality of memory banks, and a second refresh management circuit. The first refresh management circuit is configured to manage a number of times refresh is performed for the first and third plurality of memory banks, and the second refresh management circuit is configured to manage a number of times refresh is performed for the second and fourth plurality of memory banks.

Abstract: A method of training a memory device is provided. In first to third DCA training steps, a score for each of first to third DCA code combinations is calculated based on an eye window size of a data signal, and in response to a tie occurring among scores, a DCA code combination is selected based on the sum of an even-eye window minimum value and an odd-eye window minimum value of the data signal.

Abstract: An organic light emitting diode and an organic light emitting device including the same are discussed. The organic light emitting diode can include a first compound represented by a following formula, a second compound as a p-type host, and a third compound as an n-type host in an emitting material layer. As a result, the organic light emitting diode and the organic light emitting device have advantages in the driving voltage, the luminous efficiency and the lifespan.

Abstract: An organic light emitting diode and an organic light emitting device including the organic light emitting diode are discussed. The organic light emitting diode can include a first compound represented by the following formula, a second compound as a p-type host and a third compound as an n-type host in an emitting material layer. As a result, the organic light emitting diode and the organic light emitting device have advantages in the driving voltage, the luminous efficiency and the lifespan.

Abstract: A memory device with a computation function includes a first cell array including first memory cells connected to word lines, a second cell array including second memory cells connected to the word lines, a first bit line sense amplifier that sense first voltages of first bit lines connected to the first memory cells, a second bit line sense amplifier that senses second voltages of second bit lines connected to the second memory cells, a first column selection circuit that outputs a first output signal among the first voltages based on a first column compute selection signal, a second column selection circuit that outputs a second output signal among the second voltages based on a second column compute selection signal different from the first column compute selection signal, and a column compute control circuit that generates the first column compute selection signal and the second column compute selection signal.

Abstract: An organic light emitting diode and an organic light emitting device including the same are discussed. The organic light emitting diode can include a first compound represented by a following formula, a second compound as a p-type host, and a third compound as an n-type host in an emitting material layer. As a result, the organic light emitting diode and the organic light emitting device have advantages in the driving voltage, the luminous efficiency and the lifespan.

Abstract: A memory device according to an embodiment includes a memory cell array including a plurality of memory cells disposed in a plurality of rows, a register configured to store row addresses corresponding to the plurality of rows and access counts for the plurality of rows, and a refresh controller configured to determine a refresh address based on the stored row addresses and a refresh command being received, and change a refresh period for a target row based on the refresh address being associated with a previously performed refresh for the target row and the access count for a row corresponding to the target row being reached a threshold value.

Abstract: An organic light emitting diode and an organic light emitting device including the same are discussed. The organic light emitting diode can include a first electrode, a second electrode facing the first electrode, and a first emitting part including a green emitting material layer and positioned between the first and second electrodes. The green emitting material layer can include a first host, a second host and a dopant, wherein at least one of the first host and the second host is deuterated.

Abstract: An organic light emitting display device can include a first substrate including red, green and blue subpixel regions, a thin film transistor disposed on the first substrate and including a semiconductor layer including an oxide semiconductor material, a gate electrode, a source electrode, and a drain electrode, a planarization layer on the thin film transistor, and an organic light emitting diode on the planarization layer, and including a first electrode, an emitting layer, and a second electrode, the emitting layer including at least three emitting parts and charge generation layers disposed between the at least three emitting parts. Also, an encapsulation layer can be disposed on the organic light emitting diode, and include a first inorganic layer, an organic layer disposed on the first inorganic layer, and a second inorganic layer disposed on the organic layer, and a color filter can be disposed on the organic light emitting diode.

Abstract: Disclosed is a memory device communicating with a host device. The memory device may comprise a plurality of memory banks, a mode register array including a plurality of mode registers, a first mode register buffer, including a first plurality of buffer bit fields, configured to load raw data provided from a target mode register, which is one of the plurality of mode registers, to the first plurality of buffer bit fields in response to a first command received from the host device, and an input/output circuit configured to output one or more target bits stored in the first plurality of buffer bit fields to the host device in response to a second command received from the host device.

Abstract: According to embodiments of the present disclosure, an operation method of a memory device including a memory bank, which includes a plurality of edge memory cell arrays and a plurality of internal memory cell arrays arranged between the plurality of edge memory cell arrays may be provided. The operation method may comprise receiving a fine-grained refresh command, identifying a refresh target pointer value for a refresh target determination list, which includes a plurality of row addresses for the memory bank, identifying a pointed row address corresponding to the refresh target pointer value, among the plurality of row addresses, determining a first memory cell array type corresponding to the pointed row address, and performing a first refresh operation for a refresh target number of fine-grained refresh target row addresses, wherein the refresh target number is determined based on the first memory cell array type.

Abstract: There is provided a host device communicating with a memory device including a first memory bank. The host device includes a command issuance circuit configured to issue a regular refresh command for a first memory bank of a memory device at every regular refresh period, a first debit counter configured to manage a first debit count for a first sub-bank in the first memory bank, a second debit counter configured to manage a second debit count for a second sub-bank in the first memory bank, and a refresh scheduling circuit configured to determine whether to skip issuing the regular refresh command of the command issuance circuit based on the first debit count and the second debit count.

Abstract: The present disclosure relates to operation methods of a memory device including multiple rows each including multiple memory cells. One example method includes receiving an active command for a first row from a memory controller, reading a first count from a per-row hammer tracking (PRHT) region of the first row, updating the first count to generate a first updated count, comparing the first updated count with one of first and second thresholds to generate a comparison result, wherein when the first row is adjacent to the given row, the first updated count is compared with the first threshold and when the first row is not adjacent to the given row, the first updated count is compared with the second threshold, outputting a target row address based on the comparison result, and performing a row hammer mitigation operation on a row corresponding to the target row address.

Abstract: An organic light emitting diode and an organic light emitting device including the same are discussed. The organic light emitting diode can include a first electrode, a second electrode facing the first electrode, and a first emitting part including a green emitting material layer and positioned between the first and second electrodes. The green emitting material layer can include a first host, a second host and a dopant, wherein at least one of the first host and the second host is deuterated.

Abstract: An apparatus for adaptively adjusting refresh timing of a CIM based on eDRAM includes a replica array including a plurality of replica MAC arrays, each having replica cells arranged in a direction and number according to the direction and number in which memory cells performing MAC operations together in a CIM cell array are arranged and a refresh determination module that compares voltage levels of signals output from each of the plurality of replica MAC arrays with MAC operation results according to weights stored in replica cells of the plurality of replica MAC arrays and activates a refresh enable signal for refreshing memory cells of the CIM cell array.

Abstract: A memory device includes a memory bank including a plurality of memory cells and a bank register corresponding to the memory bank. The memory bank includes a main data region that stores user data and a metadata region that stores metadata corresponding to the user data. The bank register includes a metadata register that caches the metadata to be stored in the metadata region and a dirty bitmap including location information where the metadata is to be stored in the metadata region.

Abstract: An eDRAM cell for a CIM according to the present disclosure includes a first transistor which is connected between a read word line and a read bit line and has a gate connected to a storage node; a second transistor which is connected between a write bit line and the storage node and has a gate connected to a write word line; a first capacitor connected between the storage node and a ground; a third transistor which is connected between a local MAC bit line and a fourth transistor and has a gate connected to the storage node; and a fourth transistor which is connected between the third transistor and the ground and has a gate connected to a MAC word line.

Abstract: An operation method of a memory controller, which is configured to control a memory module including a plurality of memory devices and at least one error correction code (ECC) device, is provided. The method includes reading a data set including user data stored in the plurality of memory devices and ECC data stored in the at least one ECC device, based on a read command and a first address, and writing uncorrectable data in a memory area, which is included in each of the plurality of memory devices and the at least one ECC device and corresponds to the first address, when an error of the user data is not corrected based on the ECC data.

Abstract: A memory device with a computation function includes a first cell array including first memory cells connected to word lines, a second cell array including second memory cells connected to the word lines, a first bit line sense amplifier that sense first voltages of first bit lines connected to the first memory cells, a second bit line sense amplifier that senses second voltages of second bit lines connected to the second memory cells, a first column selection circuit that outputs a first output signal among the first voltages based on a first column compute selection signal, a second column selection circuit that outputs a second output signal among the second voltages based on a second column compute selection signal different from the first column compute selection signal, and a column compute control circuit that generates the first column compute selection signal and the second column compute selection signal.

Abstract: A memory device according to an embodiment includes a memory cell array including a plurality of memory cells disposed in a plurality of rows, a register configured to store row addresses corresponding to the plurality of rows and access counts for the plurality of rows, and a refresh controller configured to determine a refresh address based on the stored row addresses and a refresh command being received, and change a refresh period for a target row based on the refresh address being associated with a previously performed refresh for the target row and the access count for a row corresponding to the target row being reached a threshold value.