Patents by Inventor Do Hong Kim

Do Hong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250065188
    Abstract: Disclosed herein is an apparatus and method for counting repetitive movements based on Artificial Intelligence. The method may include generating standard movement information that includes a key pose extracted from a demonstration movement image stream based on human skeleton information, which is a set of pieces of positional information of human joints, and major joint information in the key pose and counting repetitive movements depending on whether a user movement matches the standard movement information based on human skeleton information of a user movement image stream.
    Type: Application
    Filed: February 1, 2024
    Publication date: February 27, 2025
    Inventors: Do-Hyung KIM, Jae-Hong KIM, Young-Woo YOON, Ho-Beom JEON
  • Patent number: 12198747
    Abstract: A memory includes: a plurality of word lines; and a row circuit configured to: activate at least one word line among the word lines to an active voltage level during an active operation and discharge the activated word line during a precharge operation; and discharge the word line from the active voltage level to a precharge voltage level in different manners during the precharge operation in response to a precharge command and during the precharge operation during a refresh operation.
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: January 14, 2025
    Assignee: SK hynix Inc.
    Inventors: Sang Hyun Ku, Do Hong Kim, Min Ho Seok, Duck Hwa Hong, So Yoon Kim
  • Publication number: 20240395291
    Abstract: Disclosed is a semiconductor device including a first cell mat including memory cells connected to a first bit line, a second cell mat including memory cells connected to a second bit line, a sense amplifier configured to amplify a difference in voltages between the first bit line and the second bit line, and a control circuit configured to differently adjust timing at which the first bit line and the second bit line are connected to or disconnected from the sense amplifier.
    Type: Application
    Filed: September 25, 2023
    Publication date: November 28, 2024
    Applicant: SK hynix Inc.
    Inventors: Do Hong KIM, Kwang Soo KIM, Duck Hwa HONG
  • Publication number: 20240312503
    Abstract: A memory device includes a plurality of word lines; and a row control circuit configured to: drive, in response to a precharge command, a selected word line of the word lines such that a voltage level of the selected word line decreases from a first voltage level to a second voltage level during a first section, stays at the second voltage level during a second section and decreases from the second voltage level to a third voltage level during a third section, and keep the second section at a preset time amount, or change the second section to a time amount defined by an input of an active command according to a mode control signal.
    Type: Application
    Filed: July 25, 2023
    Publication date: September 19, 2024
    Inventors: Sang Hyun KU, Do Hong KIM, Duck Hwa HONG, Min Ho SEOK, So Yoon KIM
  • Publication number: 20240161806
    Abstract: A memory includes: a plurality of word lines; and a row circuit configured to: activate at least one word line among the word lines to an active voltage level during an active operation and discharge the activated word line during a precharge operation; and discharge the word line from the active voltage level to a precharge voltage level in different manners during the precharge operation in response to a precharge command and during the precharge operation during a refresh operation.
    Type: Application
    Filed: February 2, 2023
    Publication date: May 16, 2024
    Inventors: Sang Hyun KU, Do Hong Kim, Min Ho Seok, Duck Hwa Hong, So Yoon Kim
  • Patent number: 11295799
    Abstract: A device for performing a refresh operation includes a row control circuit and a row decoder. The row control circuit is configured to generate a bank active signal and a row address for controlling an active operation for a first memory bank based on a refresh signal. The row control circuit is also configured to generate the bank active signal for controlling the active operation for a second memory bank based on a power control signal. The row decoder is configured to receive the bank active signal and the row address to control the active operation for the first memory bank and the second memory bank.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: April 5, 2022
    Assignee: SK hynix Inc.
    Inventors: Kyung Mook Kim, Do Hong Kim, Woongrae Kim, Sang Il Park, Sang Woo Yoon, Jong Seok Han
  • Publication number: 20210327493
    Abstract: A device for performing a refresh operation includes a row control circuit and a row decoder. The row control circuit is configured to generate a bank active signal and a row address for controlling an active operation for a first memory bank based on a refresh signal. The row control circuit is also configured to generate the bank active signal for controlling the active operation for a second memory bank based on a power control signal. The row decoder is configured to receive the bank active signal and the row address to control the active operation for the first memory bank and the second memory bank.
    Type: Application
    Filed: July 16, 2020
    Publication date: October 21, 2021
    Applicant: SK hynix Inc.
    Inventors: Kyung Mook KIM, Do Hong KIM, Woongrae KIM, Sang Il PARK, Sang Woo YOON, Jong Seok HAN
  • Patent number: 10706908
    Abstract: A semiconductor memory device includes: first to Nth memory banks each including a normal cell region coupled to normal word lines and a redundant cell region coupled to redundant word lines; first to Nth non-volatile memories that correspond to the first to Nth memory banks, respectively, each including a plurality of memory sets for programming repair addresses of the corresponding memory banks; a refresh control circuit for generating first to Nth count values by counting a number of the memory sets used in the first to Nth non-volatile memories, and generating a redundant reset signal based on the first to Nth count values; and an address generation circuit for sequentially generating normal addresses for selecting the normal word lines and redundant addresses for selecting the redundant word lines based on a refresh signal, and initializing the redundant addresses based on the redundant reset signal.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventor: Do-Hong Kim
  • Publication number: 20190279706
    Abstract: A semiconductor memory device includes: first to Nth memory banks each including a normal cell region coupled to normal word lines and a redundant cell region coupled to redundant word lines; first to Nth non-volatile memories that correspond to the first to Nth memory banks, respectively, each including a plurality of memory sets for programming repair addresses of the corresponding memory banks; a refresh control circuit for generating first to Nth count values by counting a number of the memory sets used in the first to Nth non-volatile memories, and generating a redundant reset signal based on the first to Nth count values; and an address generation circuit for sequentially generating normal addresses for selecting the normal word lines and redundant addresses for selecting the redundant word lines based on a refresh signal, and initializing the redundant addresses based on the redundant reset signal.
    Type: Application
    Filed: September 28, 2018
    Publication date: September 12, 2019
    Inventor: Do-Hong KIM
  • Patent number: 9627096
    Abstract: A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein N is a natural number.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: April 18, 2017
    Assignee: SK Hynix Inc.
    Inventors: No-Guen Joo, Do-Hong Kim, Jae-Il Kim
  • Publication number: 20160293243
    Abstract: A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein N is a natural number.
    Type: Application
    Filed: September 15, 2015
    Publication date: October 6, 2016
    Inventors: No-Guen JOO, Do-Hong KIM, Jae-Il KIM
  • Patent number: 9214220
    Abstract: A semiconductor memory apparatus includes a control signal generation unit configured to generate a control signal according to a mode control signal and a refresh signal; a first sense amplifier driving voltage generation unit configured to generate a first sense amplifier driving voltage according to the control signal, a first sense amplifier enable signal and a switching control signal; a switching control unit configured to generate the switching control signal according to the control signal and a second sense amplifier enable signal; a second sense amplifier driving voltage generation unit configured to generate a second sense amplifier driving voltage according to the second sense amplifier enable signal; and a switching unit configured to electrically couple or decouple output nodes of the first sense amplifier driving voltage generation unit and the second sense amplifier driving voltage generation unit according to the switching control signal.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: December 15, 2015
    Assignee: SK Hynix Inc.
    Inventor: Do Hong Kim