Patents by Inventor Do Hong Kim
Do Hong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250095478Abstract: Disclosed herein are an apparatus and method for providing crosswalk pedestrian guidance based on an image and a beacon. The method for providing crosswalk pedestrian guidance based on an image and a beacon may include estimating a walking location based on a beacon signal corresponding to at least one traffic light and first-person view sensor information, analyzing a hazard factor around a pedestrian based on an image acquired from a camera corresponding to the traffic light, predicting a hazard around the pedestrian in combination by considering together the walking location, the hazard factor, and status information of the traffic light, and providing walking guidance to a pedestrian guidance terminal based on the predicted hazard around the pedestrian.Type: ApplicationFiled: May 29, 2024Publication date: March 20, 2025Inventors: Byung-Ok HAN, Do-Hyung KIM, Jae-Hong KIM, Woo-Han YUN
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Patent number: 12248947Abstract: A banking processing method according is performed by a processing logic including an application for banking processing implemented on a user terminal and a computer-readable storage medium. The method comprises the steps of: when the application for banking processing is run, searching a hardware security area of the user terminal and confirming the existence of a certificate for confirming an execution history of the application for banking processing; when the existence of the certificate is confirmed, searching the security area and confirming the existence of a token key for identifying whether login information of the user has been set; when the existence of the token key is not confirmed, setting the login information of the user by providing a membership page for setting the login information of the user; and opening an account according to a request of the user whose login information has been set.Type: GrantFiled: March 25, 2019Date of Patent: March 11, 2025Assignee: KAKAOBANK CORP.Inventors: Jung Hee Ko, Tae Ki Ha, Yeun Su Koo, Bo Hyun Oh, Lee Rang Park, Sung Jun Kim, Ji Hong Park, Dong Joon Lee, Jung Min Ahn, Geun Won Mo, Hyeong Jin Jang, Jun Hyuk Yun, Hack Cheon Kim, Eun Jung Gil, Ji Eun Kim, Tae Won Kim, Seung Jin Lee, Do Young Lee
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Publication number: 20250065188Abstract: Disclosed herein is an apparatus and method for counting repetitive movements based on Artificial Intelligence. The method may include generating standard movement information that includes a key pose extracted from a demonstration movement image stream based on human skeleton information, which is a set of pieces of positional information of human joints, and major joint information in the key pose and counting repetitive movements depending on whether a user movement matches the standard movement information based on human skeleton information of a user movement image stream.Type: ApplicationFiled: February 1, 2024Publication date: February 27, 2025Inventors: Do-Hyung KIM, Jae-Hong KIM, Young-Woo YOON, Ho-Beom JEON
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Patent number: 12198747Abstract: A memory includes: a plurality of word lines; and a row circuit configured to: activate at least one word line among the word lines to an active voltage level during an active operation and discharge the activated word line during a precharge operation; and discharge the word line from the active voltage level to a precharge voltage level in different manners during the precharge operation in response to a precharge command and during the precharge operation during a refresh operation.Type: GrantFiled: February 2, 2023Date of Patent: January 14, 2025Assignee: SK hynix Inc.Inventors: Sang Hyun Ku, Do Hong Kim, Min Ho Seok, Duck Hwa Hong, So Yoon Kim
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Publication number: 20240395291Abstract: Disclosed is a semiconductor device including a first cell mat including memory cells connected to a first bit line, a second cell mat including memory cells connected to a second bit line, a sense amplifier configured to amplify a difference in voltages between the first bit line and the second bit line, and a control circuit configured to differently adjust timing at which the first bit line and the second bit line are connected to or disconnected from the sense amplifier.Type: ApplicationFiled: September 25, 2023Publication date: November 28, 2024Applicant: SK hynix Inc.Inventors: Do Hong KIM, Kwang Soo KIM, Duck Hwa HONG
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Publication number: 20240312503Abstract: A memory device includes a plurality of word lines; and a row control circuit configured to: drive, in response to a precharge command, a selected word line of the word lines such that a voltage level of the selected word line decreases from a first voltage level to a second voltage level during a first section, stays at the second voltage level during a second section and decreases from the second voltage level to a third voltage level during a third section, and keep the second section at a preset time amount, or change the second section to a time amount defined by an input of an active command according to a mode control signal.Type: ApplicationFiled: July 25, 2023Publication date: September 19, 2024Inventors: Sang Hyun KU, Do Hong KIM, Duck Hwa HONG, Min Ho SEOK, So Yoon KIM
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Publication number: 20240161806Abstract: A memory includes: a plurality of word lines; and a row circuit configured to: activate at least one word line among the word lines to an active voltage level during an active operation and discharge the activated word line during a precharge operation; and discharge the word line from the active voltage level to a precharge voltage level in different manners during the precharge operation in response to a precharge command and during the precharge operation during a refresh operation.Type: ApplicationFiled: February 2, 2023Publication date: May 16, 2024Inventors: Sang Hyun KU, Do Hong Kim, Min Ho Seok, Duck Hwa Hong, So Yoon Kim
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Patent number: 11295799Abstract: A device for performing a refresh operation includes a row control circuit and a row decoder. The row control circuit is configured to generate a bank active signal and a row address for controlling an active operation for a first memory bank based on a refresh signal. The row control circuit is also configured to generate the bank active signal for controlling the active operation for a second memory bank based on a power control signal. The row decoder is configured to receive the bank active signal and the row address to control the active operation for the first memory bank and the second memory bank.Type: GrantFiled: July 16, 2020Date of Patent: April 5, 2022Assignee: SK hynix Inc.Inventors: Kyung Mook Kim, Do Hong Kim, Woongrae Kim, Sang Il Park, Sang Woo Yoon, Jong Seok Han
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Publication number: 20210327493Abstract: A device for performing a refresh operation includes a row control circuit and a row decoder. The row control circuit is configured to generate a bank active signal and a row address for controlling an active operation for a first memory bank based on a refresh signal. The row control circuit is also configured to generate the bank active signal for controlling the active operation for a second memory bank based on a power control signal. The row decoder is configured to receive the bank active signal and the row address to control the active operation for the first memory bank and the second memory bank.Type: ApplicationFiled: July 16, 2020Publication date: October 21, 2021Applicant: SK hynix Inc.Inventors: Kyung Mook KIM, Do Hong KIM, Woongrae KIM, Sang Il PARK, Sang Woo YOON, Jong Seok HAN
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Patent number: 10706908Abstract: A semiconductor memory device includes: first to Nth memory banks each including a normal cell region coupled to normal word lines and a redundant cell region coupled to redundant word lines; first to Nth non-volatile memories that correspond to the first to Nth memory banks, respectively, each including a plurality of memory sets for programming repair addresses of the corresponding memory banks; a refresh control circuit for generating first to Nth count values by counting a number of the memory sets used in the first to Nth non-volatile memories, and generating a redundant reset signal based on the first to Nth count values; and an address generation circuit for sequentially generating normal addresses for selecting the normal word lines and redundant addresses for selecting the redundant word lines based on a refresh signal, and initializing the redundant addresses based on the redundant reset signal.Type: GrantFiled: September 28, 2018Date of Patent: July 7, 2020Assignee: SK hynix Inc.Inventor: Do-Hong Kim
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Publication number: 20190279706Abstract: A semiconductor memory device includes: first to Nth memory banks each including a normal cell region coupled to normal word lines and a redundant cell region coupled to redundant word lines; first to Nth non-volatile memories that correspond to the first to Nth memory banks, respectively, each including a plurality of memory sets for programming repair addresses of the corresponding memory banks; a refresh control circuit for generating first to Nth count values by counting a number of the memory sets used in the first to Nth non-volatile memories, and generating a redundant reset signal based on the first to Nth count values; and an address generation circuit for sequentially generating normal addresses for selecting the normal word lines and redundant addresses for selecting the redundant word lines based on a refresh signal, and initializing the redundant addresses based on the redundant reset signal.Type: ApplicationFiled: September 28, 2018Publication date: September 12, 2019Inventor: Do-Hong KIM
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Patent number: 9627096Abstract: A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein N is a natural number.Type: GrantFiled: September 15, 2015Date of Patent: April 18, 2017Assignee: SK Hynix Inc.Inventors: No-Guen Joo, Do-Hong Kim, Jae-Il Kim
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Publication number: 20160293243Abstract: A semiconductor memory device may include a memory bank having a plurality of word lines arranged at a predetermined address interval, an address latching unit suitable for storing a target address corresponding to a target word line of the plurality of word lines, and a refresh control unit suitable for performing a refresh operation on first to Nth word lines having different address intervals from the target word line based on the target address in response to a smart refresh command, wherein N is a natural number.Type: ApplicationFiled: September 15, 2015Publication date: October 6, 2016Inventors: No-Guen JOO, Do-Hong KIM, Jae-Il KIM
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Patent number: 9214220Abstract: A semiconductor memory apparatus includes a control signal generation unit configured to generate a control signal according to a mode control signal and a refresh signal; a first sense amplifier driving voltage generation unit configured to generate a first sense amplifier driving voltage according to the control signal, a first sense amplifier enable signal and a switching control signal; a switching control unit configured to generate the switching control signal according to the control signal and a second sense amplifier enable signal; a second sense amplifier driving voltage generation unit configured to generate a second sense amplifier driving voltage according to the second sense amplifier enable signal; and a switching unit configured to electrically couple or decouple output nodes of the first sense amplifier driving voltage generation unit and the second sense amplifier driving voltage generation unit according to the switching control signal.Type: GrantFiled: December 9, 2014Date of Patent: December 15, 2015Assignee: SK Hynix Inc.Inventor: Do Hong Kim