Abstract: This invention uses a plurality of bubble memory chips in a system for providing simultaneous input and output in a word or byte organized output. Each bubble memory chip has the same number of minor loops as is required for nominal memory size without the requirement for extra or redundant loops. Each bubble memory chip may have a number of faulty minor loops where the bit output is incorrect and cannot be used. However, a requirement for this system is that no two bubble memory chips may have a faulty bit or minor loop at the same major loop address location. An additional bubble memory chip is provided which will contain the correct data bits for locations corresponding to defective major loop addresses in the bubble memory chips making up the byte. A Programmable Read Only Memory (PROM) is provided and connected with a logic network to control the gating of the outputs of the bubble memory chips associated with the memory byte and the extra bubble memory chip to control the gating of the outputs.