Patents by Inventor Dolores Babaran Milo
Dolores Babaran Milo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11881434Abstract: In a described example, a method includes: forming a metal layer on a backside surface of a semiconductor wafer, the semiconductor wafer having semiconductor dies spaced apart by scribe lanes on an active surface of the semiconductor wafer opposite the backside surface; forming a layer with a modulus greater than about 4000 MPa up to about 8000 MPa over the metal layer; mounting the backside of the semiconductor wafer on a first side of a dicing tape having an adhesive; cutting through the semiconductor wafer, the metal layer, and the layer with a modulus greater than about 4000 MPa up to about 8000 MPa along scribe lanes; separating the semiconductor dies from the semiconductor wafer and from one another by stretching the dicing tape, expanding the cuts in the semiconductor wafer along the scribe lanes between the semiconductor dies; and removing the separated semiconductor dies from the dicing tape.Type: GrantFiled: April 27, 2021Date of Patent: January 23, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Connie Alagadan Esteron, Dolores Babaran Milo
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Patent number: 11749621Abstract: An electronic device includes a die attach pad with a set of cantilevered first leads for down bond connections, a set of second leads spaced apart from the die attach pad, a semiconductor die mounted to the die attach pad and enclosed by a package structure, a set of first bond wires connected between respective bond pads of the semiconductor die and at least some of the first leads, and a set of second bond wires connected between respective further bond pads of the semiconductor die and at least some of the second leads.Type: GrantFiled: December 22, 2022Date of Patent: September 5, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ernesto Pentecostes Rafael, Jr., Dolores Babaran Milo, Michael Flores Milo
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Patent number: 11742318Abstract: A gang clip includes a plurality of clips formed from a metal each having a center region oriented along a first plane and an angled clip foot having a foot height, a length and a bend angle sufficient to electrically contact a lead terminal of the leadframe to be used to form a device. Adjacent ones of the plurality of clips are joined to one another by a first tie bar also oriented along the first plane. The first tie bar extends to a saw street region located between adjacent ones of the clips. A second tie bar attached to the first tie bar is positioned in the saw street region.Type: GrantFiled: April 23, 2021Date of Patent: August 29, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dolores Babaran Milo, Ernesto Pentecostes Rafael, Jr., Michael Flores Milo
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Publication number: 20230170285Abstract: An integrated circuit (IC) package includes an interconnect comprising patches of unoxidized metal that are circumscribed by a region of roughened metal formed of oxidized metal. The IC package also includes a die mounted on the interconnect. The die is conductively coupled to at least a subset of the patches of unoxidized metal.Type: ApplicationFiled: November 29, 2021Publication date: June 1, 2023Inventors: Ruby Ann Merto Camenforte, Floro Lopez Camenforte, Dolores Babaran Milo
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Publication number: 20230129297Abstract: An electronic device includes a die attach pad with a set of cantilevered first leads for down bond connections, a set of second leads spaced apart from the die attach pad, a semiconductor die mounted to the die attach pad and enclosed by a package structure, a set of first bond wires connected between respective bond pads of the semiconductor die and at least some of the first leads, and a set of second bond wires connected between respective further bond pads of the semiconductor die and at least some of the second leads.Type: ApplicationFiled: December 22, 2022Publication date: April 27, 2023Inventors: Ernesto Pentecostes Rafael, JR., Dolores Babaran Milo, Michael Flores Milo
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Publication number: 20230054963Abstract: An integrated circuit that includes micro-etched channels on a bottom surface is provided. The integrated circuit includes a lead frame having electrically conductive contact terminal pads and a die centrally disposed in the lead frame. Wire bonds provide an electrical connection from the die to the electrically conductive contact terminal pads. A mold compound encapsulates the die and the wire bonds, where a bottom surface of the mold compound is flush with a bottom surface of the contact terminal pads. A channel is defined in the bottom surface of the mold compound around a periphery of the contact terminal pads.Type: ApplicationFiled: August 18, 2021Publication date: February 23, 2023Inventors: Dolores Babaran Milo, Michael Flores Milo
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Patent number: 11538768Abstract: An electronic device includes a die attach pad with a set of cantilevered first leads for down bond connections, a set of second leads spaced apart from the die attach pad, a semiconductor die mounted to the die attach pad and enclosed by a package structure, a set of first bond wires connected between respective bond pads of the semiconductor die and at least some of the first leads, and a set of second bond wires connected between respective further bond pads of the semiconductor die and at least some of the second leads.Type: GrantFiled: October 4, 2019Date of Patent: December 27, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Ernesto Pentecostes Rafael, Jr., Dolores Babaran Milo, Michael Flores Milo
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Publication number: 20220359352Abstract: An electronic package includes an electronic component including terminals, a plurality of leads, at least some of the leads being electrically coupled to the terminals within the electronic package, and a mold compound covering the electronic component and partially covering the leads. Each of the leads include an exposed bottom face coplanar with a bottom surface of the mold compound and an exposed end face coplanar with one of a plurality of side surfaces of the mold compound. For at least some of the leads, the exposed end face includes a narrow portion forming a concave recess, the narrow portion being between top and bottom edges of the exposed end face.Type: ApplicationFiled: May 10, 2021Publication date: November 10, 2022Inventors: Dolores Babaran Milo, Ernesto Pentecostes Rafael, JR., John Carlo Cruz Molina
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Publication number: 20220344302Abstract: A gang clip includes a plurality of clips formed from a metal each having a center region oriented along a first plane and an angled clip foot having a foot height, a length and a bend angle sufficient to electrically contact a lead terminal of the leadframe to be used to form a device. Adjacent ones of the plurality of clips are joined to one another by a first tie bar also oriented along the first plane. The first tie bar extends to a saw street region located between adjacent ones of the clips. A second tie bar attached to the first tie bar is positioned in the saw street region.Type: ApplicationFiled: April 23, 2021Publication date: October 27, 2022Inventors: Dolores Babaran Milo, Ernesto Pentecostes Rafael, JR., Michael Flores Milo
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Publication number: 20220157700Abstract: A lead frame includes a first side having a first die attach pad that is bondable to a die, and a second side that has a second die attach pad that is bondable to another die. The lead frame includes multiple leads on the edges of the lead frame to connect the die. As part of a no-leads device, such as a quad flat no leads (QFN) or dual flat no-leads (DFN), one of the die attach pads is used in binding to a die, and the other die attach pad is used for thermal dissipation and mounting to a structure such as printed circuit board (PCB).Type: ApplicationFiled: February 1, 2022Publication date: May 19, 2022Inventors: Dolores Babaran Milo, Ernesto Pentecostes Rafael
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Patent number: 11239130Abstract: A method includes performing a first molding process to enclose a portion of a first semiconductor die in a first package structure with an opening that exposes a portion of a second semiconductor die mounted to the first semiconductor die, as well as performing a deposition process to deposit a stress absorbing material in the opening of the first package structure to cover the portion of the second semiconductor die, and performing a second molding process to enclose a portion of the stress absorbing structure in a second package structure that extends on a side of the first package structure.Type: GrantFiled: October 10, 2019Date of Patent: February 1, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dolores Babaran Milo, Floro Lopez Camenforte, III, Joe Anne Feive Carbonell Lopez
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Patent number: 11211320Abstract: A semiconductor package includes a pad and leads having a planar profile shaped from a planar base metal, a semiconductor die attached to the pad, a wire bond extending from the semiconductor die to a respective lead, and mold compound covering the semiconductor die, the wire bond, and a first portion of the respective lead, wherein a second portion of the respective lead extends beyond the mold compound. A shape of the respective lead within the planar profile includes a notch indented relative to a first elongated side of the shape of the respective lead and a protrusion protruding outwardly relative to a second elongated side of the shape of the respective lead. The notch and the protrusion are each partially covered by the mold compound and partially outside the mold compound.Type: GrantFiled: December 31, 2019Date of Patent: December 28, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dolores Babaran Milo, Joe Ann Feive Carbonell Lopez, Gloria Bibal Manaois, Kevin John Bersamira Delos Santos
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Publication number: 20210249306Abstract: In a described example, a method includes: forming a metal layer on a backside surface of a semiconductor wafer, the semiconductor wafer having semiconductor dies spaced apart by scribe lanes on an active surface of the semiconductor wafer opposite the backside surface; forming a layer with a modulus greater than about 4000 MPa up to about 8000 MPa over the metal layer; mounting the backside of the semiconductor wafer on a first side of a dicing tape having an adhesive; cutting through the semiconductor wafer, the metal layer, and the layer with a modulus greater than about 4000 MPa up to about 8000 MPa along scribe lanes; separating the semiconductor dies from the semiconductor wafer and from one another by stretching the dicing tape, expanding the cuts in the semiconductor wafer along the scribe lanes between the semiconductor dies; and removing the separated semiconductor dies from the dicing tape.Type: ApplicationFiled: April 27, 2021Publication date: August 12, 2021Inventors: Connie Alagadan Esteron, Dolores Babaran Milo
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Publication number: 20210202365Abstract: A semiconductor package includes a pad and leads having a planar profile shaped from a planar base metal, a semiconductor die attached to the pad, a wire bond extending from the semiconductor die to a respective lead, and mold compound covering the semiconductor die, the wire bond, and a first portion of the respective lead, wherein a second portion of the respective lead extends beyond the mold compound. A shape of the respective lead within the planar profile includes a notch indented relative to a first elongated side of the shape of the respective lead and a protrusion protruding outwardly relative to a second elongated side of the shape of the respective lead. The notch and the protrusion are each partially covered by the mold compound and partially outside the mold compound.Type: ApplicationFiled: December 31, 2019Publication date: July 1, 2021Inventors: Dolores Babaran Milo, Joe Ann Feive Carbonell Lopez, Gloria Bibal Manaois, Kevin John Bersamira Delos Santos
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Patent number: 11049800Abstract: In a described example, a method for making a packaged semiconductor device includes laser ablating a first groove with a first width and a first depth into a mounting surface of a substrate between landing pads. A first pillar bump on an active surface of a semiconductor device is bonded to a first landing pad; and a second pillar bump on the semiconductor device is bonded to a second landing pad. A channel forms with the active surface of the semiconductor device forming a first wall of the channel, the first pillar bump forms a second wall of the channel, the second pillar bump forming a third wall of the channel, and a surface of the first groove forms a fourth wall of the channel. The channel is filled with mold compound and at least a portion of the substrate and the semiconductor device are covered with mold compound.Type: GrantFiled: February 25, 2020Date of Patent: June 29, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dolores Babaran Milo, Cherry Lyn Marquez Aranas
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Patent number: 10991621Abstract: In a described example, a method includes: forming a metal layer on a backside surface of a semiconductor wafer, the semiconductor wafer having semiconductor dies spaced apart by scribe lanes on an active surface of the semiconductor wafer opposite the backside surface; forming a layer with a modulus greater than about 4000 MPa up to about 8000 MPa over the metal layer; mounting the backside of the semiconductor wafer on a first side of a dicing tape having an adhesive; cutting through the semiconductor wafer, the metal layer, and the layer with a modulus greater than about 4000 MPa up to about 8000 MPa along scribe lanes; separating the semiconductor dies from the semiconductor wafer and from one another by stretching the dicing tape, expanding the cuts in the semiconductor wafer along the scribe lanes between the semiconductor dies; and removing the separated semiconductor dies from the dicing tape.Type: GrantFiled: August 5, 2019Date of Patent: April 27, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Connie Alagadan Esteron, Dolores Babaran Milo
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Publication number: 20210111086Abstract: A method includes performing a first molding process to enclose a portion of a first semiconductor die in a first package structure with an opening that exposes a portion of a second semiconductor die mounted to the first semiconductor die, as well as performing a deposition process to deposit a stress absorbing material in the opening of the first package structure to cover the portion of the second semiconductor die, and performing a second molding process to enclose a portion of the stress absorbing structure in a second package structure that extends on a side of the first package structure.Type: ApplicationFiled: October 10, 2019Publication date: April 15, 2021Inventors: Dolores Babaran Milo, Floro Lopez Camenforte, III, Joe Anne Feive Carbonell Lopez
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Publication number: 20210104471Abstract: An electronic device includes a die attach pad with a set of cantilevered first leads for down bond connections, a set of second leads spaced apart from the die attach pad, a semiconductor die mounted to the die attach pad and enclosed by a package structure, a set of first bond wires connected between respective bond pads of the semiconductor die and at least some of the first leads, and a set of second bond wires connected between respective further bond pads of the semiconductor die and at least some of the second leads.Type: ApplicationFiled: October 4, 2019Publication date: April 8, 2021Applicant: Texas Instruments IncorporatedInventors: Ernesto Pentecostes Rafael, JR., Dolores Babaran Milo, Michael Flores Milo
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Patent number: 10964629Abstract: A method of manufacturing a semiconductor package includes attaching semiconductor dies to an array of leadframes and positioning a clip array in alignment with the array of leadframes within a mold cavity, the clip array including clips that electrically connect to at least some of the semiconductor dies and a siderail along a perimeter of the clip array. The siderail forms a set of reliefs extending from an outer edge of the siderail to an inner edge of the siderail, the inner edge being adjacent to the array of leadframes. The method also includes injecting a mold compound into the mold cavity through a flow path including the set of reliefs of the siderail to form a mold block at least partially covering the semiconductor dies.Type: GrantFiled: January 18, 2019Date of Patent: March 30, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Dolores Babaran Milo, Richard Diestro Sumalinog, Ruby Ann Merto Camenforte, Sylvester Tigno Sanchez
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Publication number: 20210043512Abstract: In a described example, a method includes: forming a metal layer on a backside surface of a semiconductor wafer, the semiconductor wafer having semiconductor dies spaced apart by scribe lanes on an active surface of the semiconductor wafer opposite the backside surface; forming a layer with a modulus greater than about 4000 MPa up to about 8000 MPa over the metal layer; mounting the backside of the semiconductor wafer on a first side of a dicing tape having an adhesive; cutting through the semiconductor wafer, the metal layer, and the layer with a modulus greater than about 4000 MPa up to about 8000 MPa along scribe lanes; separating the semiconductor dies from the semiconductor wafer and from one another by stretching the dicing tape, expanding the cuts in the semiconductor wafer along the scribe lanes between the semiconductor dies; and removing the separated semiconductor dies from the dicing tape.Type: ApplicationFiled: August 5, 2019Publication date: February 11, 2021Inventors: Connie Alagadan Esteron, Dolores Babaran Milo