Abstract: A semiconductor die includes a transformer with terminals of a first winding electrically coupled to external die terminals of the semiconductor die. The terminals of a second winding of the transformer are coupled to internal circuitry of the semiconductor die. An ESD clamp circuit is electrically coupled to the center tap of the second winding of the transformer. When made conductive during and ESD event, the ESD clamp circuit discharges ESD current between the center tap and a supply rail.

Abstract: A semiconductor die has ESD clamp circuits that include vertical PNP transistors. The vertical PNP transistors include at least one region in a semiconductor substrate that is substrate isolated from a biased portion of the substrate. The ESD clamp circuits include a resistive element that is electrically coupled in a conductive path between the emitter and base of the vertical PNP transistor. The PNP transistor is conductive during certain ESD events to discharge ESD charge from the emitter to the collector.

Abstract: An electro-static discharge (ESD) protection system for a wireless transceiver comprises a switch circuit at a first terminal and a second terminal of a low noise amplifier; a primary ESD protection circuit between an input terminal and a low voltage supply terminal of the wireless transceiver for shunting a first source of current of an ESD event; a clamp element between a high voltage supply terminal and the low voltage supply terminal having a clamping voltage that is less than a breakdown voltage of the LNA for preventing a second source of current of the ESD event from receipt by the LNA; and a power supply ESD clamp element between the high voltage supply terminal and the low voltage supply terminal for shunting a third source of current of the ESD event at the high voltage supply terminal.

Abstract: An electrostatic-discharge (ESD) protection circuit is provided. The circuit includes an I/O terminal coupled for receiving a signal having a negative voltage relative to a voltage supply terminal. An ESD transistor is formed in an isolated well. The transistor includes a control electrode and a first current electrode coupled to the I/O terminal. The isolated well is configured as a body electrode of the transistor. An ESD diode includes an anode electrode coupled to the voltage supply terminal and a cathode electrode coupled to a second current electrode of the transistor.

Abstract: An integrated circuit (IC) is disclosed. The IC includes a pin to electrically connect the IC to an external circuit and a transistor that includes a base, a collector and an emitter. The pin is coupled to an internal circuit that is configured to operate in a preselected operating frequency range. The base is coupled to the pin and a resistor is coupled between the base and the pin. The IC further includes an electrostatic discharge (ESD) rail coupled to the pin through a first ESD diode. A second ESD diode is coupled between the floating ESD rail and a power supply to provide a second ESD current sink path.

Abstract: An integrated circuit (IC) is disclosed. The IC includes a pin to electrically connect the IC to an external circuit and a transistor that includes a base, a collector and an emitter. The pin is coupled to an internal circuit that is configured to operate in a preselected operating frequency range. The base is coupled to the pin and a resistor is coupled between the base and the pin. The IC further includes an electrostatic discharge (ESD) rail coupled to the pin through a first ESD diode. A second ESD diode is coupled between the floating ESD rail and a power supply to provide a second ESD current sink path.

Abstract: An electrostatic discharge, ESD, protection structure (200) formed within a semiconductor substrate of an integrated circuit device (600). The integrated circuit device (600) comprising: a radio frequency domain (632); a digital domain (610). The ESD protection structure (200) further includes an intermediate domain located between the radio frequency domain (632) and the digital domain (610) that comprises at least one radio frequency, RF, passive or active device that exhibits an impedance characteristic that increases as a frequency of operation increases.

Abstract: An electrostatic-discharge (ESD) protection circuit is provided. The circuit includes an I/O terminal coupled for receiving a signal having a negative voltage relative to a voltage supply terminal. An ESD transistor is formed in an isolated well. The transistor includes a control electrode and a first current electrode coupled to the I/O terminal. The isolated well is configured as a body electrode of the transistor. An ESD diode includes an anode electrode coupled to the voltage supply terminal and a cathode electrode coupled to a second current electrode of the transistor.

Abstract: This specification discloses methods for integrating a SiGe-based HBT (heterojunction bipolar transistor) and a Si-based BJT (bipolar junction transistor) together in a single manufacturing process that does not add a lot of process complexity, and an integrated circuit that can be fabricated utilizing such a streamlined manufacturing process. In some embodiments, such an integrated circuit can enjoy both the benefits of a higher RF (radio frequency) performance for the SiGe HBT and a lower leakage current for the Si-based BJT. In some embodiments, such an integrated circuit can be applied to an ESD (electrostatic discharge) clamp circuit, in order to achieve a lower, or no, yield-loss.

Abstract: This specification discloses methods for integrating a SiGe-based HBT (heterojunction bipolar transistor) and a Si-based BJT (bipolar junction transistor) together in a single manufacturing process that does not add a lot of process complexity, and an integrated circuit that can be fabricated utilizing such a streamlined manufacturing process. In some embodiments, such an integrated circuit can enjoy both the benefits of a higher RF (radio frequency) performance for the SiGe HBT and a lower leakage current for the Si-based BJT. In some embodiments, such an integrated circuit can be applied to an ESD (electrostatic discharge) clamp circuit, in order to achieve a lower, or no, yield-loss.

Abstract: An electrostatic discharge, ESD, protection structure (200) formed within a semiconductor substrate of an integrated circuit device (600). The integrated circuit device (600) comprising: a radio frequency domain (632); a digital domain (610). The ESD protection structure (200) further includes an intermediate domain located between the radio frequency domain (632) and the digital domain (610) that comprises at least one radio frequency, RF, passive or active device that exhibits an impedance characteristic that increases as a frequency of operation increases.

Abstract: A semiconductor device and method. The device includes a first domain and a second domain each having a power rail and a ground rail. The device further includes a signal line connected between the first domain and the second domain. The device also includes an electrostatic discharge protection circuit for providing cross-domain ESD protection. The protection circuit includes a blocking transistor connected between the first domain power rail and the signal line. The protection circuit also includes a power rail clamp connected between the first domain power rail and the first domain ground rail. The power rail clamp is operable to apply a control signal to a gate of the blocking transistor to switch it on during normal operation and to switch it off during an ESD event. The power rail clamp is operable during the ESD event to conduct an ESD current.

Abstract: A semiconductor device and method. The device includes a first domain and a second domain each having a power rail and a ground rail. The device further includes a signal line connected between the first domain and the second domain. The device also includes an electrostatic discharge protection circuit for providing cross-domain ESD protection. The protection circuit includes a blocking transistor connected between the first domain power rail and the signal line. The protection circuit also includes a power rail clamp connected between the first domain power rail and the first domain ground rail. The power rail clamp is operable to apply a control signal to a gate of the blocking transistor to switch it on during normal operation and to switch it off during an ESD event. The power rail clamp is operable during the ESD event to conduct an ESD current.

Abstract: An electrostatic discharge (ESD) protection device on a semiconductor substrate and a method for making the same. The device has an active region. The active region includes a gate. The active region also includes a source including a silicide portion having a source contact. The active region further includes a drain including a silicide portion having a drain contact. The source and drain each extend away from the gate along a device axis. The drain contact is laterally offset with respect to the source contact along a direction orthogonal to the device axis whereby current flow between the source contact and the drain contact has a lateral component. The device further comprises a non-silicide region located laterally between the drain contact and the source contact.

Abstract: An electrostatic discharge (ESD) protection device on a semiconductor substrate and a method for making the same. The device has an active region. The active region includes a gate. The active region also includes a source including a silicide portion having a source contact. The active region further includes a drain including a silicide portion having a drain contact. The source and drain each extend away from the gate along a device axis. The drain contact is laterally offset with respect to the source contact along a direction orthogonal to the device axis whereby current flow between the source contact and the drain contact has a lateral component. The device further comprises a non-silicide region located laterally between the drain contact and the source contact.