Patents by Inventor Domagoj Siprak
Domagoj Siprak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230337213Abstract: A central trajectory controller including a cell interface configured to establish signaling connections with one or more backhaul moving cells and to establish signaling connections with one or more outer moving cells, an input data repository configured to obtain input data related to a radio environment of the one or more outer moving cells and the one or more backhaul moving cells, and a trajectory processor configured to determine, based on the input data, first coarse trajectories for the one or more backhaul moving cells and second coarse trajectories for the one or more outer moving cells, the cell interface further configured to send the first coarse trajectories to the one or more backhaul moving cells and to send the second coarse trajectories to the one or more outer moving cells.Type: ApplicationFiled: March 13, 2023Publication date: October 19, 2023Inventors: Biljana BADIC, Steven A. BOWERS, Yang-Seok CHOI, Miltiadis FILIPPOU, Bertram GUNZELMANN, Nageen HIMAYAT, Ingolf KARLS, Nirlesh Kumar KOSHTA, Rajkumar KRISHNAPERUMAL, Markus Dominik MUECK, Hosein NIKOPOUR, Pradeep PANGI, Jerome PARRON, Bernhard RAAF, Sabine ROESSEL, Dario SABELLA, Bernd SCHALLER, Domagoj SIPRAK, Christopher STOBART, Shashanka TOTADAMANE RAMAPPA, Sudeep MANITHARA VAMANAN, Zhibin YU, Jing ZHU
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Patent number: 11641644Abstract: A central trajectory controller including a cell interface configured to establish signaling connections with one or more backhaul moving cells and to establish signaling connections with one or more outer moving cells, an input data repository configured to obtain input data related to a radio environment of the one or more outer moving cells and the one or more backhaul moving cells, and a trajectory processor configured to determine, based on the input data, first coarse trajectories for the one or more backhaul moving cells and second coarse trajectories for the one or more outer moving cells, the cell interface further configured to send the first coarse trajectories to the one or more backhaul moving cells and to send the second coarse trajectories to the one or more outer moving cells.Type: GrantFiled: March 26, 2020Date of Patent: May 2, 2023Assignee: Intel CorporationInventors: Biljana Badic, Steven A. Bowers, Yang-Seok Choi, Miltiadis Filippou, Bertram Gunzelmann, Nageen Himayat, Ingolf Karls, Nirlesh Kumar Koshta, Rajkumar Krishnaperumal, Markus Dominik Mueck, Hosein Nikopour, Pradeep C Pangi, Jerome Parron, Bernhard Raaf, Sabine Roessel, Dario Sabella, Bernd Schaller, Domagoj Siprak, Christopher Stobart, Shashanka Totadamane Ramappa, Sudeep Manithara Vamanan, Zhibin Yu, Jing Zhu
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Patent number: 11552030Abstract: An integrated circuit structure includes a first metallization layer with first and second electrodes, each of which has electrode fingers. A second metallization layer may be included below the first metallization layer and include one or more electrodes with electrode fingers. The integrated circuit structure is configured to exhibit at least partial vertical inductance cancellation when the first electrode and second electrode are energized. The integrated circuit structure can be configured to also exhibit horizontal inductance cancellation between adjacent electrode fingers. Also disclosed is a simulation model that includes a capacitor model that models capacitance between electrode fingers having a finger length and includes at least one resistor-capacitor series circuit in which a resistance of the resistor increases with decreasing finger length for at least some values of the finger length.Type: GrantFiled: July 31, 2018Date of Patent: January 10, 2023Assignee: Intel CorporationInventors: Daniel Sira, Domagoj Siprak, Jonas Fritzin
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Patent number: 11545586Abstract: A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.Type: GrantFiled: September 29, 2017Date of Patent: January 3, 2023Assignee: Intel CorporationInventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
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Publication number: 20220353650Abstract: Disclosed herein is a communication device for vehicular radio communications. The communication device includes one or more processors configured to identify a plurality of vehicular communication devices that form a cluster of cooperating vehicular communication devices. The one or more processors also determine channel resource allocations for the plurality of vehicular communication devices that includes channel resources allocated for a first vehicular radio communication technology and channel resources allocated for a second vehicular radio communication technology. The one or more processors also transmit the channel resource allocation to the plurality of vehicular communication devices.Type: ApplicationFiled: November 26, 2021Publication date: November 3, 2022Inventors: Carlos ALDANA, Biljana BADIC, Dave CAVALCANTI, Debabani CHOUDHURY, Christian DREWES, Jong-Kae FWU, Bertram GUNZELMANN, Nageen HIMAYAT, Ingolf KARLS, Duncan KITCHIN, Markus Dominik MUECK, Bernhard RAAF, Domagoj SIPRAK, Harry SKINNER, Christopher STOBART, Shilpa TALWAR, Zhibin YU
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Publication number: 20220320350Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.Type: ApplicationFiled: June 23, 2022Publication date: October 6, 2022Applicant: Intel CorporationInventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
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Patent number: 11424354Abstract: A Group III-Nitride (III-N) device structure is provided comprising: a heterostructure having three or more layers comprising III-N material, an anode n+ region and a cathode comprising donor dopants, wherein the anode n+ region and the cathode are on the first layer of the heterostructure and wherein the anode n+ region and the cathode extend beyond the heterostructure, and an anode metal region within a recess that extends through two or more of the layers, wherein the anode metal region is in electrical contact with the first layer, wherein the anode metal region comprises a first width within the recess and a second width beyond the recess, and wherein the anode metal region is coupled with the anode n+ region. Other embodiments are also disclosed and claimed.Type: GrantFiled: September 29, 2017Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger
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Patent number: 11380806Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.Type: GrantFiled: September 28, 2017Date of Patent: July 5, 2022Assignee: Intel CorporationInventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
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Patent number: 11380755Abstract: Capacitors are disclosed. A capacitor includes a plate-to-plate capacitor and a finger-to-finger capacitor. The plate-to-plate capacitor includes at least a first plate and a second plate. The second plate is in proximity to the first plate. The finger to finger capacitor is in proximity to the first plate. The finger to finger capacitor includes a first plurality of finger elements and a second plurality of finger elements. The second plurality of finger elements is interleaved with the first plurality of finger elements. The first plurality of finger elements is electrically connected to the first plate and the second plurality of finger elements is electrically connected to the second plate. The second plurality of finger elements and the first plate form additional plate-to-plate capacitors.Type: GrantFiled: December 18, 2017Date of Patent: July 5, 2022Assignee: Intel CorporationInventors: Domagoj Siprak, Jonas Fritzin, Sundaravadanan Anantha Krishnan
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Patent number: 11373995Abstract: A Group III-Nitride (III-N) device structure is presented comprising: a heterostructure having three or more layers comprising III-N material, a cathode comprising donor dopants, wherein the cathode is on a first layer of the heterostructure, an anode within a recess that extends through two or more of the layers of the heterostructure, wherein the anode comprises a first region wherein the anode is separated from the heterostructure by a high k dielectric material, and a second region wherein the anode is in direct contact with the heterostructure, and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.Type: GrantFiled: September 29, 2017Date of Patent: June 28, 2022Assignee: Intel CorporationInventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
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Publication number: 20200411699Abstract: A Group III-Nitride (III-N) device structure is provided which comprises: a heterostructure having three or more layers comprising III-N material, an anode within a recess that extends through two or more of the layers, wherein the anode is in electrical contact with the first layer, a cathode comprising donor dopants, wherein the cathode is on the first layer of the heterostructure; and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 29, 2017Publication date: December 31, 2020Applicant: INTEL CORPORATIONInventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
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Publication number: 20200411505Abstract: A Group III-Nitride (III-N) device structure is presented comprising: a heterostructure having three or more layers comprising material, a cathode comprising donor dopants, wherein the cathode is on a first layer of the heterostructure, an anode within a recess that extends through two or more of the layers of the heterostructure, wherein the anode comprises a first region wherein the anode is separated from the heterostructure by a high k dielectric material, and a second region wherein the anode is in direct contact with the heterostructure, and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 29, 2017Publication date: December 31, 2020Applicant: INTEL CORPORATIONInventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
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Publication number: 20200279908Abstract: Capacitors are disclosed. A capacitor includes a plate-to-plate capacitor and a finger-to-finger capacitor. The plate-to-plate capacitor includes at least a first plate and a second plate. The second plate is in proximity to the first plate. The finger to finger capacitor is in proximity to the first plate. The finger to finger capacitor includes a first plurality of finger elements and a second plurality of finger elements. The second plurality of finger elements is interleaved with the first plurality of finger elements. The first plurality of finger elements is electrically connected to the first plate and the second plurality of finger elements is electrically connected to the second plate. The second plurality of finger elements and the first plate form additional plate-to-plate capacitors.Type: ApplicationFiled: December 18, 2017Publication date: September 3, 2020Inventors: Domagoj SIPRAK, Jonas FRITZIN, Sundaravadanan ANANTHA KRISHNAN
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Publication number: 20200229206Abstract: A central trajectory controller including a cell interface configured to establish signaling connections with one or more backhaul moving cells and to establish signaling connections with one or more outer moving cells, an input data repository configured to obtain input data related to a radio environment of the one or more outer moving cells and the one or more backhaul moving cells, and a trajectory processor configured to determine, based on the input data, first coarse trajectories for the one or more backhaul moving cells and second coarse trajectories for the one or more outer moving cells, the cell interface further configured to send the first coarse trajectories to the one or more backhaul moving cells and to send the second coarse trajectories to the one or more outer moving cells.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Inventors: Biljana BADIC, Steven A. BOWERS, Yang-Seok CHOI, Miltiadis FILIPPOU, Bertram GUNZELMANN, Nageen HIMAYAT, Ingolf KARLS, Nirlesh Kumar KOSHTA, Rajkumar KRISHNAPERUMAL, Markus Dominik MUECK, Hosein NIKOPOUR, Pradeep C. PANGI, Jerome PARRON, Bernhard RAAF, Sabine ROESSEL, Dario SABELLA, Bernd SCHALLER, Domagoj SIPRAK, Christopher STOBART, Shashanka T R, Sudeep VAMANAN, Zhibin YU, Jing ZHU
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Publication number: 20200220030Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.Type: ApplicationFiled: September 28, 2017Publication date: July 9, 2020Applicant: INTEL CORPORATIONInventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
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Publication number: 20200203518Abstract: A Group III-Nitride (III-N) device structure is provided comprising: a heterostructure having three or more layers comprising III-N material, an anode n+ region and a cathode comprising donor dopants, wherein the anode n+ region and the cathode are on the first layer of the heterostructure and wherein the anode n+ region and the cathode extend beyond the heterostructure, and an anode metal region within a recess that extends through two or more of the layers, wherein the anode metal region is in electrical contact with the first layer, wherein the anode metal region comprises a first width within the recess and a second width beyond the recess, and wherein the anode metal region is coupled with the anode n+ region. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: September 29, 2017Publication date: June 25, 2020Applicant: Santa ClaraInventors: Harald Gossner, Peter Baumgartner, Uwe Hodel, Domagoj Siprak, Stephan Leuschner, Richard Geiger
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Publication number: 20200043874Abstract: An integrated circuit structure includes a first metallization layer with first and second electrodes, each of which has electrode fingers. A second metallization layer may be included below the first metallization layer and include one or more electrodes with electrode fingers. The integrated circuit structure is configured to exhibit at least partial vertical inductance cancellation when the first electrode and second electrode are energized. The integrated circuit structure can be configured to also exhibit horizontal inductance cancellation between adjacent electrode fingers. Also disclosed is a simulation model that includes a capacitor model that models capacitance between electrode fingers having a finger length and includes at least one resistor-capacitor series circuit in which a resistance of the resistor increases with decreasing finger length for at least some values of the finger length.Type: ApplicationFiled: July 31, 2018Publication date: February 6, 2020Applicant: INTEL IP CORPORATIONInventors: Daniel Sira, Domagoj Siprak, Jonas Fritzin
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Patent number: 9654108Abstract: One embodiment described is an apparatus that includes an active device structured in a semiconductor body. The semiconductor body may include a gate terminal to receive a switched bias signal, and a bulk terminal to receive a forward body-bias signal. A first circuit portion may be coupled to the gate terminal to provide the switched bias signal, and a second circuit portion may be coupled to the bulk terminal to provide the forward body-bias signal.Type: GrantFiled: January 11, 2008Date of Patent: May 16, 2017Assignee: Intel Mobile Communications GmbHInventors: Domagoj Siprak, Marc Tiebout
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Patent number: 9583595Abstract: Disclosed herein are Lateral Diffused Metal Oxide Semiconductor (LDMOS) device and trench isolation related devices, methods, and techniques. In one illustration, a doped region is formed within a semiconductor substrate. A trench isolation region is formed within the doped region. The doped region and the trench isolation region are part of a Lateral Diffused Metal Oxide Semiconductor (LDMOS) device. The trench isolation region or an interface between the trench isolation region and the doped region is configured to reduce low frequency noise in the LDMOS device.Type: GrantFiled: September 2, 2015Date of Patent: February 28, 2017Assignee: Infineon Technologies AGInventors: Giovanni Calabrese, Domagoj Siprak, Wolfgang Molzer, Uwe Hodel
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Publication number: 20150380522Abstract: Disclosed herein are Lateral Diffused Metal Oxide Semiconductor (LDMOS) device and trench isolation related devices, methods, and techniques. In one illustration, a doped region is formed within a semiconductor substrate. A trench isolation region is formed within the doped region. The doped region and the trench isolation region are part of a Lateral Diffused Metal Oxide Semiconductor (LDMOS) device. The trench isolation region or an interface between the trench isolation region and the doped region is configured to reduce low frequency noise in the LDMOS device.Type: ApplicationFiled: September 2, 2015Publication date: December 31, 2015Inventors: Giovanni Calabrese, Domagoj Siprak, Wolfgang Molzer, Uwe Hodel