Patents by Inventor Domenico Murabito

Domenico Murabito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9627472
    Abstract: An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: April 18, 2017
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Domenico Murabito, Angelo Magri'
  • Patent number: 9324803
    Abstract: A method for manufacturing a semiconductor power device, comprising the steps of: forming a trench in a semiconductor body having a first type of conductivity; partially filling the trench with semiconductor material via epitaxial growth so as to obtain a first column having a second type of conductivity and having an internal cavity. The epitaxial growth includes simultaneously supplying a gas containing dopant ions of the second type of conductivity, hydrochloric acid HCl in gaseous form and dichlorosilane DCS in gaseous form, so that the ratio between the amount of HCl and the amount of DCS has a value of from 3.5 to 5.5.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: April 26, 2016
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Giuseppe Morale, Carlo Magro, Domenico Murabito, Tiziana Cuscani
  • Publication number: 20150349052
    Abstract: An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.
    Type: Application
    Filed: August 12, 2015
    Publication date: December 3, 2015
    Inventors: Mario Giuseppe SAGGIO, Domenico MURABITO, Angelo MAGRI'
  • Publication number: 20140346588
    Abstract: A method for manufacturing a semiconductor power device, comprising the steps of: forming a trench in a semiconductor body having a first type of conductivity; partially filling the trench with semiconductor material via epitaxial growth so as to obtain a first column having a second type of conductivity and having an internal cavity. The epitaxial growth includes simultaneously supplying a gas containing dopant ions of the second type of conductivity, hydrochloric acid HCl in gaseous form and dichlorosilane DCS in gaseous form, so that the ratio between the amount of HCl and the amount of DCS has a value of from 3.5 to 5.5.
    Type: Application
    Filed: May 20, 2014
    Publication date: November 27, 2014
    Applicant: STMICROELECTRONICS S.r.l.
    Inventors: Giuseppe MORALE, Carlo MAGRO, Domenico MURABITO, Tiziana CUSCANI
  • Patent number: 8039898
    Abstract: An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top surface and inside an active portion of the body; and forming an edge-termination structure. The edge-termination structure is formed by: a ring region having the first type of conductivity and a first doping level, set within a peripheral edge portion of the body and electrically coupled to the active region; and a guard region, having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface and connecting the active region to the ring region.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: October 18, 2011
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Mario Giuseppe Saggio, Domenico Murabito, Ferruccio Frisina
  • Publication number: 20110049638
    Abstract: An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.
    Type: Application
    Filed: August 25, 2010
    Publication date: March 3, 2011
    Applicant: STMICROELECTRONICS S.R.L.
    Inventors: Mario Giuseppe SAGGIO, Domenico MURABITO, Angelo MAGRI'
  • Patent number: 7790520
    Abstract: An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top surface and inside an active portion of the body; and forming an edge-termination structure. The edge-termination structure is formed by: a ring region having the first type of conductivity and a first doping level, set within a peripheral edge portion of the body and electrically connected to the active region; and a guard region, having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface and connecting the active region to the ring region.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: September 7, 2010
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Mario Giuseppe Saggio, Domenico Murabito, Ferruccio Frisina
  • Publication number: 20100093136
    Abstract: An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top surface and inside an active portion of the body; and forming an edge-termination structure. The edge-termination structure is formed by: a ring region having the first type of conductivity and a first doping level, set within a peripheral edge portion of the body and electrically connected to the active region; and a guard region, having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface and connecting the active region to the ring region.
    Type: Application
    Filed: December 17, 2009
    Publication date: April 15, 2010
    Applicant: STMicroelectronics, S.r.l.
    Inventors: Mario Giuseppe Saggio, Domenico Murabito, Ferruccio Frisina
  • Publication number: 20080001223
    Abstract: An embodiment of a process for manufacturing a semiconductor power device envisages the steps of: providing a body made of semiconductor material having a first top surface; forming an active region with a first type of conductivity in the proximity of the first top surface and inside an active portion of the body; and forming an edge-termination structure. The edge-termination structure is formed by: a ring region having the first type of conductivity and a first doping level, set within a peripheral edge portion of the body and electrically connected to the active region; and a guard region, having the first type of conductivity and a second doping level, higher than the first doping level, set in the proximity of the first top surface and connecting the active region to the ring region.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 3, 2008
    Inventors: Mario Saggio, Domenico Murabito, Ferruccio Frisina