Abstract: A low-noise preamplifier stage, in particular for magnetic heads, which comprises an input stage comprising a differential circuit and a single-transistor output stage, wherein the differential stage has an intrinsic offset voltage, is ground-connectable and can be directly coupled to the magnetic head, the two transistors forming the differential circuit having different bias currents in order to reduce the input equivalent noise, the base terminal of the first transistor of the differential circuit defining an input of the stage which can be connected directly to a terminal of the magnetic head, the other terminal of the head being connected directly to the ground, the base terminal of the other transistor of the different circuit being connected to the intermediate point of a pair of resistors which are mutually connected in series between the single transistor of the output stage and a line at reference voltage, so that the differential stage biases the output with its offset voltage without requiring add

Abstract: A current source circuit capable of generating two currents of opposite polarities. In order to generate the two currents, the circuit comprises a current source stage including a current mirror and feeding a first output current and an inverter stage connected to the source stage and generating a second output current with opposite polarity with respect to the first. The inverter stage comprises a current mirror and a variable current source defining a control electrode. In order to eliminate the differences in the amplitude of the output currents, the inverter stage comprises a memory element connected to the control electrode so as to store an electrode controlling signal. Switch elements are furthermore interposed between the first output and the second output so as to short-circuit them during the trimming step so that the two output currents are equal to one another while the memory element memorizes the control signal. This signal remains stored during the normal operation of the circuit.

Abstract: The circuit comprises a tank capacitance and a charge circuit supplied with the same voltage as the bridge and comprising an inductance and a control transistor. There is also provided a control circuit, which comprises an oscillator controlling the periodic switching of control transistor and a comparator which controls the momentary clamping of control transistor in the condition wherein the charge circuit is interrupted when the difference between the voltage across capacitance and the power supply voltage exceeds a preset maximum value and the unclamping of the same transistor when such difference falls below a preset minimum value. A further comparator similarly clamps control transistor if there is an excess current in the transistor itself.

Abstract: A multipurpose integrated circuit for driving in a switching mode an externally connected load or loads permits implementation of any appropriate supply scheme of the external load or loads through six output terminals thereof and is therefore useful in a large number of applications. The integrated circuit uses six integrated power switching devices provided with respective recirculation diodes and a single externally connected sensing resistor for generating, by means of a customary PWM control loop, a control signal by which means of a logic circuit configurable by progrmaming permits the generation of driving signals as a function of the control signal for all six integrated power switches in accordance with a configuration of the driving signals which conforms with the particular scheme of connection of the load or loads selected among the different bridge type and unipolar-motor type schemes which may be selected by programming.

Abstract: In this MOS-transistor bridge circuit, for obtaining a fast flyback conduction of the current after a normal operation of the circuit, instead of the flyback diodes associated with each transistor of the bridge, the MOS transistors themselves are employed, driven so as to conduct current from the ground to the power supply, that is in the opposite direction with respect to that of normal operation. For this purpose a control section is provided receiving at the input a fast flyback signal and comprising delay gates connected to the disable inputs of the transistors, so as to delay switching off thereof, and to maintain in the on state two diagonally opposed transistors so as to allow current to flow from the ground to the power supply through these diagonally opposed transistors and the load until the current decreases to zero.

Abstract: The circuit controls current switching in multiple inductive loads (L1, L2, L3, L4) fed by means of respective switching switches (SW1, SW2, SW3, SW4) and by means of respective current adjustment switches (SWA, SWB), and comprises a single sense resistor (R) in series to said switching switches, and a single comparator circuit (C, FF) adapted to generate a logical signal (Q) when the voltage across the sense resistor exceeds a reference voltage (V.sub.ref), which drives a plurality of AND gates (PA, PB) which control said adjustment switches and the second inputs whereof are driven by respective square-wave signals in opposite phase with a period equal to twice the switching period.

Abstract: A circuit for holding a MOS power transistor in a conduction state on the occurrence of an outage in the voltage supply, being of a type which comprises a first MOS transistor having its source connected to a line of the voltage supply and its drain connected to the gate of the power transistor, further comprises a diode connected between the drain of the first transistor and the gate of the power transistor, and a second transistor of the MOS type having its gate connected to the gate of the first transistor drain connected to the gate of the power transistor. The circuit prevents the gate capacitance of the power transistor from becoming discharged on a failure of the voltage supply, thus holding that transistor in a conducting state.

Abstract: A circuit for sensing the magnitude and sense of a current flowing through the load of an H-bridge stage driving the load in a switching mode by means of a clocked, square-wave driving signal and the inverted signal thereof applied, respectively, to two pairs of analog switches arranged in a bridge configuration and functionally switching the load between a supply node and a virtual ground node is made by utilizing a single sensing resistance connected between the virtual ground node and the real ground node of the circuit, the signal across the resistance and the inverted signal thereof are fed to two inputs of an analog multiplex whose output signal is fed to the input of a comparator in order to obtain at the output of the latter a signal with an amplitude proportional to the intensity of the current and a polarity determined by the polarity of a reference voltage which is applied to another input of the comparator.

Abstract: A CMOS logic circuit for sampling data coming from TTL logic circuits under frequency control by a system's clock intrinsically faster than prior art similar circuits is obtained by combining a TTL/CMOS compatibility interface inverting stage with a first stage of the sampling circuit (master or latch stage). The circuit of the invention permits elimination of two inverters and therefore reduction of data transfer delay.

Abstract: This charge pump circuit comprises a capacitor connected with a first terminal thereof to a reference voltage point through a first switch element and with a second terminal thereof to a switching section. The switching section, which is arranged between a positive supply voltage line and the ground, is controlled so as to alternately and selectively connect the second terminal of the capacitor to the positive supply and to ground. The first terminal of the capacitor is further connected to the gate of the MOS transistor to be driven. During operation the switch section is controlled so as to alternately charge the capacitor and allow transfer of the charge of the capacitor to the MOS transistor gate, thereby achieving a fast charging of the MOS transistor and a low circuit dissipation in the DC mode.

Abstract: This circuit, for reliably driving a load both in DC and AC mode with a low dissipation, comprises a pair of MOS power transistors, in a push-pull configuration, and a bootstrap circuit including a bootstrap capacitor placed between the source of the upper MOS transistor and a reference voltage point, through a first switch. A second switch is arranged between the supply line and the gate of the upper MOS transistor, while a third switch is arranged between the gate of the upper MOS transistor and the point common to the first switch and the bootstrap capacitor. During DC operation, the switches are open or closed in order to allow for the connection of the gate of the MOS power transistor to the supply voltage. During AC operation, the switches are controlled thereby, alternately the capacitor is charged at the voltage of the reference voltage point and the upper MOS transistor is held at a gate-to-source voltage sufficient to feed the load.