Abstract: A semiconductor structure, a system, and a method of forming a multi-silicide structure for stacked FETs within the semiconductor. The semiconductor structure may include an NFET. The semiconductor structure may also include a PFET. The semiconductor structure may also include an NFET silicide proximately connected to the NFET, where the NFET silicide is a first material. The semiconductor structure may also include a PFET silicide proximately connected to the PFET, where the PFET silicide is a second material different than the first material. The system may include the semiconductor structure. The method may include forming an NFET silicide proximately connected to an NFET, where the NFET silicide is a first material. The method may also include forming a PFET silicide proximately connected to a PFET, where the PFET silicide is a second material different than the first material.

Abstract: A semiconductor structure having two different trench isolation structures is provided. The first trench isolation structure is located in a space between each neighboring pair of first conductivity type field effect transistors (FETs) and between each neighboring pair of second conductivity type FETs. The second trench isolation structure is located in a space between each neighboring pair of first conductivity type FETs and second conductivity type FETs. The first and second trench isolations structures are designed to have different widths and contain compositionally different trench dielectric materials.

Abstract: A semiconductor device integrated circuit includes a semiconductor wafer, an insulator on the wafer, a first field effect transistor (FET) positioned in the insulator, a second FET positioned in the insulator between the wafer and the first FET, a pore in the insulator that extends to the second FET, a via that is electrically connected to the second FET and positioned in the pore, and a liner positioned between the via and the pore. The first FET is electrically insulated from the via by the liner.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a niobium-based silicide layer. An IC structure according to the disclosure includes a transistor on a substrate, the transistor including a gate structure above the substrate and a source/drain (S/D) region on the substrate adjacent the gate structure. A niobium-based silicide layer is on at least an upper surface the S/D region of the transistor, and extends across substantially an entire width of the S/D region. An S/D contact to the S/D region is in contact with the niobium-based silicide layer.

Abstract: Structures that include a Bragg grating and methods of fabricating a structure that includes a Bragg grating. The structure includes a waveguide core and a Bragg grating having a plurality of segments positioned with a spaced arrangement adjacent to the waveguide core. Each segment includes one or more exterior surfaces. The structure further includes a silicide layer located on the one or more exterior surfaces of each segment.

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a niobium-based silicide layer. An IC structure according to the disclosure includes a transistor on a substrate, the transistor including a gate structure above the substrate and a source/drain (S/D) region on the substrate adjacent the gate structure. A niobium-based silicide layer is on at least an upper surface the S/D region of the transistor, and extends across substantially an entire width of the S/D region. An S/D contact to the S/D region is in contact with the niobium-based silicide layer.

Abstract: A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.

Abstract: Methods of forming a metal resistor are provided. The methods may include: depositing a metal layer, e.g., tungsten, on a substrate; and forming the metal resistor by implanting a semiconductor species, e.g., silicon and/or germanium, into the metal layer to form a semiconductor-metal alloy layer from at least a portion of the metal layer. In certain embodiments, an adhesion layer may be deposited by ALD prior to metal layer depositing. The metal resistor has a sheet resistance that remains substantially constant prior to and after subsequent annealing.

Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by implanting nitrogen into the structure.

Abstract: A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.

Abstract: A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.

Abstract: A method for forming a precision resistor or an e-fuse structure where tungsten silicon is used. The tungsten silicon layer is modified by changing the crystalline structure to a tetragonal tungsten silicon layer.

Abstract: A semiconductor device includes a metal thin film such as an eFUSE or a precision resistor above and laterally displaced from an interconnect structure. A first dielectric layer is disposed over the interconnect structure and optionally under the metal thin film, and is adapted to prevent etching of the interconnect structure during patterning of the metal thin film. Contacts to the metal thin film and the interconnect are made through a second dielectric layer that is disposed over the metal thin film and over the interconnect.

Abstract: A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.

Abstract: During a physical vapor deposition (PVD) process, the ion energy of a depositing species is controlled. By varying the ion energy throughout the process, the degree of conformality of the deposited layer over three-dimensional structures, including the extent to which the deposited layer merges between adjacent structures can be controlled.

Abstract: During a physical vapor deposition (PVD) process, the ion energy of a depositing species is controlled. By varying the ion energy throughout the process, the degree of conformality of the deposited layer over three-dimensional structures, including the extent to which the deposited layer merges between adjacent structures can be controlled.

Abstract: A method of forming a titanium nitride (TiN) diffusion barrier includes exposing a deposition surface to a first pulse of a titanium-containing precursor and to a first pulse of a nitrogen-rich plasma to form a first TiN layer with a first nitrogen concentration making a lower portion of the TiN diffusion barrier, the first nitrogen concentration of the first TiN layer is increased by the first pulse of the nitrogen-rich plasma reducing a reactivity of the lower portion of the TiN diffusion barrier to prevent fluorine diffusion. The first TiN layer is exposed to second pulses of the titanium-containing precursor and the nitrogen-rich plasma to form a second TiN layer with a second nitrogen concentration above the first TiN layer making an upper portion of the TiN diffusion barrier, the first pulse of the nitrogen-rich plasma has a substantially longer duration than the second pulse of the nitrogen-rich plasma.

Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.

Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.

Abstract: A method of forming an electrical contact in an integrated circuit, and an integrated circuit are disclosed. In an embodiment, the integrated circuit comprises a substrate, an insulating layer, and a metal layer. An opening is formed through the insulating layer to expose an active area of the substrate. The metal layer forms a cusp at a top end of the opening, narrowing this end of the opening. In embodiments, the method comprises depositing a conductive layer in the opening to form a liner, applying a filler material inside the opening to protect a portion of the liner, removing the cusp to widen the top of the opening while the filler material protects the portion of the liner covered by this material, removing the filler material from the opening, re-lining the opening, and filling the opening with a conductive material to form a contact through the insulating layer.