Abstract: A semiconductor device integrated circuit includes a semiconductor wafer, an insulator on the wafer, a first field effect transistor (FET) positioned in the insulator, a second FET positioned in the insulator between the wafer and the first FET, a pore in the insulator that extends to the second FET, a via that is electrically connected to the second FET and positioned in the pore, and a liner positioned between the via and the pore. The first FET is electrically insulated from the via by the liner.

Abstract: A semiconductor device includes a top source/drain region, a bottom source/drain region, and a conductive layer over a top surface and upper half of sidewalls of the bottom source/drain region. A length of the bottom source/drain region is larger than a length of the top source/drain region.

Abstract: A semiconductor structure that includes the top field-effect transistor (FET) on a portion of the bottom FET. The semiconductor structure includes the middle dielectric isolation where the middle dielectric isolation is over the top surface of the gate of the bottom FET. The isolation layer connects the sidewalls of adjacent portions of the middle dielectric isolation. The isolation layer vertically separates one or more top source/drains of the top FET from one or more bottom source/drains of the bottom FET. A first air gap is over the middle portion of the bottom source/drain and between the middle portion of the bottom source/drain and the middle portion of the isolation. A second air gap is below the middle portion of the top source/drain and between the middle portion of the top source/drain and the middle portion of the isolation layer.

Abstract: A semiconductor structure, a system, and a method of forming a multi-silicide structure for stacked FETs within the semiconductor. The semiconductor structure may include an NFET. The semiconductor structure may also include a PFET. The semiconductor structure may also include an NFET silicide proximately connected to the NFET, where the NFET silicide is a first material. The semiconductor structure may also include a PFET silicide proximately connected to the PFET, where the PFET silicide is a second material different than the first material. The system may include the semiconductor structure. The method may include forming an NFET silicide proximately connected to an NFET, where the NFET silicide is a first material. The method may also include forming a PFET silicide proximately connected to a PFET, where the PFET silicide is a second material different than the first material.

Abstract: A semiconductor structure having two different trench isolation structures is provided. The first trench isolation structure is located in a space between each neighboring pair of first conductivity type field effect transistors (FETs) and between each neighboring pair of second conductivity type FETs. The second trench isolation structure is located in a space between each neighboring pair of first conductivity type FETs and second conductivity type FETs. The first and second trench isolations structures are designed to have different widths and contain compositionally different trench dielectric materials.

Abstract: A semiconductor device integrated circuit includes a semiconductor wafer, an insulator on the wafer, a first field effect transistor (FET) positioned in the insulator, a second FET positioned in the insulator between the wafer and the first FET, a pore in the insulator that extends to the second FET, a via that is electrically connected to the second FET and positioned in the pore, and a liner positioned between the via and the pore. The first FET is electrically insulated from the via by the liner.

Abstract: Structures that include a Bragg grating and methods of fabricating a structure that includes a Bragg grating. The structure includes a waveguide core and a Bragg grating having a plurality of segments positioned with a spaced arrangement adjacent to the waveguide core. Each segment includes one or more exterior surfaces. The structure further includes a silicide layer located on the one or more exterior surfaces of each segment.