Abstract: A plural clock system for multiple processor configurations is provided which comprises one clock system for each processor. Each pre-synchronized clock system has a strobe unit and multi-phase output generator. Each multi-phase output generator has a strobe input signal, a plurality of phase output signals and an expansion sync output signal. One of the clock systems employs its oscillator as the master oscillator for the master plural clock system and the other pre-synchronized clock systems are coupled to, and synchronized by the expansion sync output signals of other clock systems.