Abstract: Methods and systems for resolving the lock point ambiguity for the GPS receiver are disclosed. The method involves generation of the absolute lock point data bit by the reference station receiver, transmission of the absolute data bit to the rover receiver, and comparison between the raw lock point data with the absolute lock point data bit in the rover receiver. The system employs the reference station receiver, the rover receiver, and the communication link.

Abstract: The effect of the multipath distortions on the carrier phase measurements is reduced by using the weighted correlation functions. The generators of both periodic and dynamic weighted functions are used. The apparatus and method employing generators of such weighted functions can comprise the standard correlators and/or the weighted function correlators.

Abstract: An apparatus combining a handheld, electronic video game device, a location determination receiver, an electronic map and/or electronic yellow pages, and geocoding. The apparatus provides a user with his location and locations of map features and/or yellow page addresses proximate to his location. The handheld, electronic video game display displays the user's location and a map and/or yellow pages and hosts a memory cartridge that includes software for a user interface, for maps and/or yellow pages database, and for geocoding. The apparatus benefits from the high manufacturing and sales volumes of existing handheld games devices.

Abstract: A GPS receiver having a rapid acquisition of a GPS satellite signal when a normal operational mode is entered after a low power standby mode. The GPS receiver includes an RF section for receiving the GPS satellite signal and providing an GPS IF signal, a correlator section for providing a correlation signal for the correlation between the GPS IF signal and an internally generated replica signal, and a microprocessor section for receiving the correlation signal and calculating a geographical location of the GPS receiver. The replica signal is based upon a reference frequency from a reference oscillator and a reference time of arrival (TOA) from a timer. In order to increase acquisition speed, the microprocessor section provides the correlator section with an initial frequency adjustment and an initial TOA adjustment to correct for drift in the reference frequency during the standby mode.

Abstract: A GPS receiver having a rapid acquisition of a GPS satellite signal when a normal operational mode is entered after a low power standby mode. The GPS receiver includes an RF section for receiving the GPS satellite signal and providing an GPS IF signal, a correlator section for providing a correlation signal for the correlation between the GPS IF signal and a GPS replica signal, and a microprocessor section for receiving the correlation signal and calculating a geographical location of the GPS receiver. The GPS replica signal is based upon a reference frequency from a reference oscillator and a reference time from a timer. In the standby mode, the operation of the RF section, correlator section, and microprocessor section is inhibited while the reference oscillator and time continue to operate.

Abstract: A GPS receiver having a normal mode to receive GPS satellite signals and to provide location information, and a low power standby mode. A microprocessor system in the GPS receiver causes the GPS receiver to alternate between the normal mode and the low power standby mode in order to reduce the average power consumption in the GPS receiver. In the normal mode a GPS antenna receives GPS satellite signals, the GPS frequency downconverter converts the frequency of the GPS satellite signals to an intermediate frequency, a digital signal processing system processes the intermediate frequency to provide GPS satellite signal correlation information. The microprocessor system processes the correlation information and provides location information to a user. In the standby mode, the operating power is inhibited in the GPS antenna and the GPS frequency downconverter, the system clock is inhibited in the digital processing system, and the microprocessor clock is inhibited in the microprocessor system.