Patents by Inventor Dominic Go
Dominic Go has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8566485Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.Type: GrantFiled: August 3, 2012Date of Patent: October 22, 2013Assignee: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Ruchi Wadhawan
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Patent number: 8495257Abstract: In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.Type: GrantFiled: October 20, 2010Date of Patent: July 23, 2013Assignee: Apple Inc.Inventors: Shailendra S. Desai, Mark D. Hayter, Dominic Go
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Patent number: 8443118Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.Type: GrantFiled: July 31, 2012Date of Patent: May 14, 2013Assignee: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Puneet Kumar
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Patent number: 8417844Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.Type: GrantFiled: May 17, 2012Date of Patent: April 9, 2013Assignee: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Ruchi Wadhawan
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Publication number: 20130042155Abstract: A system, apparatus, and method for writing trace data to storage. Trace data is captured from one or more processors, and then the trace data is written to a trace buffer. The trace data includes program counters of instructions executed by the processors and other debug data. A direct memory access (DMA) controller in a non-real-time block of the system reads trace data from the trace buffer and then writes the trace data to memory via a non-real-time port of a memory controller.Type: ApplicationFiled: August 11, 2011Publication date: February 14, 2013Inventors: Timothy J. Millet, Shun Wai "Dominic" Go, Conrad H. Ziesler
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Publication number: 20120297096Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.Type: ApplicationFiled: July 31, 2012Publication date: November 22, 2012Inventors: Dominic Go, Mark D. Hayter, Puneet Kumar
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Publication number: 20120297097Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.Type: ApplicationFiled: August 3, 2012Publication date: November 22, 2012Applicant: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Ruchi Wadhawan
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Publication number: 20120233360Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.Type: ApplicationFiled: May 17, 2012Publication date: September 13, 2012Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Ruchi Wadhawan
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Patent number: 8266338Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.Type: GrantFiled: October 19, 2011Date of Patent: September 11, 2012Assignee: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Puneet Kumar
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Patent number: 8209446Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.Type: GrantFiled: August 30, 2011Date of Patent: June 26, 2012Assignee: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Ruchi Wadhawan
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Publication number: 20120036289Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.Type: ApplicationFiled: October 19, 2011Publication date: February 9, 2012Inventors: Dominic Go, Mark D. Hayter, Puneet Kumar
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Publication number: 20110314186Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.Type: ApplicationFiled: August 30, 2011Publication date: December 22, 2011Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Ruchi Wadhawan
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Publication number: 20110307759Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.Type: ApplicationFiled: August 24, 2011Publication date: December 15, 2011Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Weichun Ku
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Patent number: 8069279Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit circuit and a data flow control circuit coupled to the transmit circuit. The transmit circuit is configured to perform DMA transfers, each DMA transfer described by a DMA descriptor stored in a data structure in memory. There is a data structure for each DMA channel that is in use. The data flow control circuit is configured to control the transmit circuit's processing of DMA descriptors for each DMA channel responsive to data flow control data in the DMA descriptors in the corresponding data structure.Type: GrantFiled: March 5, 2007Date of Patent: November 29, 2011Assignee: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Puneet Kumar
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Patent number: 8032670Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.Type: GrantFiled: January 29, 2010Date of Patent: October 4, 2011Assignee: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Ruchi Wadhawan
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Patent number: 8028103Abstract: In one embodiment, a direct memory access (DMA) controller comprises a transmit control circuit, an offload engine, and a receive control circuit. The transmit control circuit is configured to read first DMA data from an address space in a host. Coupled to receive the first DMA data from the transmit control circuit, the offload engine is configured to perform at least a first operation on the first DMA data to produce a result. The offload engine is configured to at least start performing the first operation during a DMA transfer that provides the first DMA data to the offload engine. Coupled to the offload engine to receive the result, the receive control circuit is configured to write the result to the address space in the host according to a DMA descriptor data structure that describes the DMA transfer.Type: GrantFiled: September 22, 2009Date of Patent: September 27, 2011Assignee: Apple Inc.Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Weichun Ku
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Publication number: 20110035459Abstract: In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.Type: ApplicationFiled: October 20, 2010Publication date: February 10, 2011Inventors: Shailendra S. Desai, Mark D. Hayter, Dominic Go
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Patent number: 7836220Abstract: In one embodiment, a system comprises at least a first node and a second node coupled to a network. The second node comprises a local memory and a direct memory access (DMA) controller coupled to the local memory. The first node is configured to transmit at least a first packet to the second node to access data in the local memory and at least one other packet that is not coded to access the local memory. The second node is configured to capture the packet from a data link layer of a protocol stack, and wherein the DMA controller is configured to perform one more transfers with the local memory to access the data specified by the first packet responsive to the first packet received from the data link layer. The second node is configured to process the other packet to a top of the protocol stack.Type: GrantFiled: August 17, 2006Date of Patent: November 16, 2010Assignee: Apple Inc.Inventors: Shailendra S. Desai, Mark D. Hayter, Dominic Go
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Publication number: 20100131680Abstract: In one embodiment, an apparatus comprises a first interface circuit, a direct memory access (DMA) controller coupled to the first interface circuit, and a host coupled to the DMA controller. The first interface circuit is configured to communicate on an interface according to a protocol. The host comprises at least one address space mapped, at least in part, to a plurality of memory locations in a memory system of the host. The DMA controller is configured to perform DMA transfers between the first interface circuit and the address space, and the DMA controller is further configured to perform DMA transfers between a first plurality of the plurality of memory locations and a second plurality of the plurality of memory locations.Type: ApplicationFiled: January 29, 2010Publication date: May 27, 2010Inventors: Dominic Go, Mark D. Hayter, Zongjian Chen, Ruchi Wadhawan
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Patent number: 7707477Abstract: In one embodiment, a checksum generator comprises an N-bit accumulator and a plurality of N-bit 3:2 carry save adders. A first plurality of the plurality of N-bit 3:2 carry save adders are coupled to receive N-bit inputs extracted from an input to the checksum generator, and one of the first plurality has an N-bit input coupled to the output of the accumulator. A second plurality of the plurality of N-bit 3:2 carry save adders have inputs coupled to outputs of the first plurality, and a most significant bit of each carry output of the first plurality is inserted as a least significant bit of the carry output at the input to the second plurality.Type: GrantFiled: September 29, 2005Date of Patent: April 27, 2010Assignee: Apple Inc.Inventors: Dominic Go, Daniel C. Murray