Abstract: A video decoding apparatus for decoding an encoded video bitstream having frames of video data encoded in rows of macroblocks. The video decoding apparatus comprises a parsing unit configured to receive the encoded video bitstream and to interpret the encoded video bitstream to generate items of macroblock information to be used for reconstructing the video frames of video data. The parsing unit is configured to store the items of macroblock information in a memory in bitstream order. The video decoding apparatus further comprises a line control unit configured to generate line control information associated with each row of macroblocks, the line control information comprising a sequence of pointers to the items of macroblock information stored in the memory, such that sequentially reading the sequence of pointers accesses the items of macroblock information in raster scan order. The line control information is stored in said memory in association with said items of macroblock information.

Abstract: A data processing apparatus is provided for performing video decoding operations on blocks of video data, the data processing apparatus comprising: a programmable inverse transform unit configured to perform an inverse transform operation on a set of input values in response to a sequence of instructions, the programmable inverse transform unit comprising a first execution path and a second execution path arranged to perform data operations to implement the inverse transform operation, wherein the data operations performed by the first and second execution path are configured in dependence on the sequence of instructions, wherein the programmable inverse transform unit is configured to operate in a first mode in which each instruction in the sequence of instructions is interpreted using a first instruction length and causes the first execution path and the second execution path to be configured independently of each other, and the programmable inverse transform unit is configured to operate in a second mode i

Abstract: A data processing system 2 includes an instruction decoder 22 responsive to polynomial divide instructions DIVL.PN to generate control signals that control processing circuitry 26 to perform a polynomial division operation. The denominator polynomial is represented by a denominator value stored within a register with an assumption that the highest degree term of the polynomial always has a coefficient of “1” such that this coefficient need not be stored within the register storing the denominator value and accordingly the denominator polynomial may have a degree one higher than would be possible with the bit space within the register storing the denominator value alone. The polynomial divide instruction returns a quotient value and a remainder value respectively representing the quotient polynomial and the remainder polynomial.

Abstract: A data processing apparatus is provided for performing video decoding operations on blocks of video data, the data processing apparatus comprising: a programmable inverse transform unit configured to perform an inverse transform operation on a set of input values in response to a sequence of instructions, the programmable inverse transform unit comprising a first execution path and a second execution path arranged to perform data operations to implement the inverse transform operation, wherein the data operations performed by the first and second execution path are configured in dependence on the sequence of instructions, wherein the programmable inverse transform unit is configured to operate in a first mode in which each instruction in the sequence of instructions is interpreted using a first instruction length and causes the first execution path and the second execution path to be configured independently of each other, and the programmable inverse transform unit is configured to operate in a second mode i

Abstract: A video decoding apparatus for decoding an encoded video bitstream having frames of video data encoded in rows of macroblocks. The video decoding apparatus comprises a parsing unit configured to receive the encoded video bitstream and to interpret the encoded video bitstream to generate items of macroblock information to be used for reconstructing the video frames of video data. The parsing unit is configured to store the items of macroblock information in a memory in bitstream order. The video decoding apparatus further comprises a line control unit configured to generate line control information associated with each row of macroblocks, the line control information comprising a sequence of pointers to the items of macroblock information stored in the memory, such that sequentially reading the sequence of pointers accesses the items of macroblock information in raster scan order. The line control information is stored in said memory in association with said items of macroblock information.

Abstract: A data processing system 2 includes an instruction decoder 22 responsive to polynomial divide instructions DIVL.PN to generate control signals that control processing circuitry 26 to perform a polynomial division operation. The denominator polynomial is represented by a denominator value stored within a register with an assumption that the highest degree term of the polynomial always has a coefficient of “1” such that this coefficient need not be stored within the register storing the denominator value and accordingly the denominator polynomial may have a degree one higher than would be possible with the bit space within the register storing the denominator value alone. The polynomial divide instruction returns a quotient value and a remainder value respectively representing the quotient polynomial and the remainder polynomial.