Patents by Inventor Dominic Joseph Schepis

Dominic Joseph Schepis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SOI MOSFETS exhibiting reduced floating-body effects
    Patent number: 7163866
    Abstract: Disadvantages of the floating body of a SOI MOSFET are addressed by providing a pocket halo implant of indium beneath the gate and in the channel region of the semiconductor SOI layer of the MOSFET. Also provided is the method for fabricating the device.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: January 16, 2007
    Assignee: International Business Machines Corporation
    Inventors: Fariborz Assaderaghi, Werner Rausch, Dominic Joseph Schepis, Ghavam G. Shahidi
  • SOI MOSFETS exhibiting reduced floating-body effects
    Publication number: 20040142515
    Abstract: Disadvantages of the floating body of a SOI MOSFET are addressed by providing a pocket halo implant of indium beneath the gate and in the channel region of the semiconductor SOI layer of the MOSFET. Also provided is the method for fabricating the device.
    Type: Application
    Filed: December 11, 2003
    Publication date: July 22, 2004
    Applicant: IBM Corporation (Fishkill)
    Inventors: Fariborz Assaderaghi, Werner Rausch, Dominic Joseph Schepis, Ghavam G. Shahidi
  • SOI MOSFETS exhibiting reduced floating-body effects
    Patent number: 6686629
    Abstract: Disadvantages of the floating body of a SOI MOSFET are addressed by providing a pocket halo implant of indium beneath the gate and in the channel region of the semiconductor SOI layer of the MOSFET. Also provided is the method for fabricating the device.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: February 3, 2004
    Assignee: International Business Machines Corporation
    Inventors: Fariborz Assaderaghi, Werner Rausch, Dominic Joseph Schepis, Ghavam G. Shahidi
  • Method of fabricating a multistack 3-dimensional high density semiconductor device
    Patent number: 6451634
    Abstract: A multistack 3-D semiconductor structure comprising a first level structure comprising a first semiconductor substrate and first active devices; and a second level structure comprising a SOI semiconductor structure bonded to the first level structure and further comprising second active devices; and wherein the first active devices are more heat tolerant than the second active devices is provided along with a method for its fabrication.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: September 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: William Hsioh-Lien Ma, Dominic Joseph Schepis
  • Multistack 3-dimensional high density semiconductor device and method for fabrication
    Patent number: 6291858
    Abstract: A multistack 3-D semiconductor structure comprising a first level structure comprising a first semiconductor substrate and first active devices; and a second level structure comprising a SOI semiconductor structure bonded to the first level structure and further comprising second active devices; and wherein the first active devices are more heat tolerant than the second active devices is provided along with a method for its fabrication.
    Type: Grant
    Filed: January 3, 2000
    Date of Patent: September 18, 2001
    Assignee: International Business Machines Corporation
    Inventors: William Hsioh-Lien Ma, Dominic Joseph Schepis
  • Method and structure for front-side gettering of silicon-on-insulator substrates
    Patent number: 5646053
    Abstract: A method of gettering an SOI wafer from the front side of the wafer includes depositing a gettering layer, such as polysilicon, on the SOI layer and annealing the SOI wafer with the gettering layer in place. A polish stop structure, which can be deposited before or after the gettering layer, provides a means for selectively removing the gettering layer from the SOI wafer without damaging the surface or eroding the thickness of the SOI layer.
    Type: Grant
    Filed: December 20, 1995
    Date of Patent: July 8, 1997
    Assignee: International Business Machines Corporation
    Inventors: Dominic Joseph Schepis, Joseph Francis Shepard