Abstract: Fan-Out Wafer Level Packages (FO-WLPs) include double-sided molded package bodies in which first and second layers of components are embedded in a back-to-back relationship. In one embodiment, the FO-WLP fabrication method includes positioning a first microelectronic component carried by a first temporary substrate in a back-to-back relationship with a second microelectronic component carried by a second temporary substrate. The first and second components are overmolded while positioned in the back-to-back relationship to produce a double-sided molded package body. The first temporary substrate is then removed to expose a first principal surface of the package body at which the first component is exposed, and the second temporary substrate is likewise removed to expose a second, opposing principal surface of the package body at which the second component is exposed.

Abstract: An integrated circuit (IC) die has an active side and an inactive side, opposite the active side. A recess is formed within the interior of the inactive side and extends partially through the integrated circuit towards the active side. The IC die is part of a packaged IC device, where the die is attached to a package component such as a lead frame, substrate, or another die, using die attach adhesive that fills the recess, thereby providing a more reliable bond between the IC die and the package component.

Abstract: A semiconductor device includes a semiconductor die having first and second opposing main surfaces and a die bonding pads on the first main surface, and a conductive member having first and second opposing main surfaces that surrounds the die. The die and the conductive member are encapsulated with a first encapsulant and form an expanded die. The expanded die is mounted on a lead frame having conductive leads, and the conductive leads are electrically coupled to the conductive member, which acts as a power bar, and to the die bonding pads. The conductive member also is electrically coupled to at least one of the die bonding pads. The expanded die and portions of the conductive leads are encapsulated with a second encapsulant.

Abstract: A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.

Abstract: A method of assembling Redistributed Chip Package (RCP) semiconductor devices. An active die structure is encapsulated in a molding compound with internal electrical contacts of the active die structure positioned at an active face of an encapsulation layer. A dummy die structure is positioned at a back face of the encapsulation layer. A redistribution layer is formed at an active face of the encapsulation layer. The redistribution layer includes a layer of insulating material and redistribution electrical interconnections. The insulating material is built up with grooves along saw streets. External electrical contacts exposed at a surface of the redistribution layer are connected with the redistribution electrical interconnections. The dummy die structure is removed and then the semiconductor devices are singulated.

Abstract: A method of packaging a semiconductor die includes the use of an embedded ground plane or drop-in embedded unit. The embedded unit is a single, stand-alone unit with at least one cavity. The embedded unit is placed on and within an encapsulation area of a process mounting surface. The embedded unit may have different sizes and shapes and a number of different cavities that can be placed in a predetermined position on a substrate, panel or tape during processing of semiconductor dies that are embedded into redistributed chip package (RCP) or wafer level package (WFL) panels. The embedded unit provides the functionality and design flexibility to run a number of embedded units and semiconductor dies or components having different sizes and dimensions in a single processing panel or batch and reduces die drift, movement or skew during encapsulation and post-encapsulation cure.