Patents by Inventor Dominic Lane

Dominic Lane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240125718
    Abstract: Methods and systems include generating, from an electron beam generator, an electron beam in a vacuum chamber. A mounting platform in the vacuum chamber is configured to support a material. The electron beam is directed at a surface region of the material at a grazing angle. A detector assembly, which may have an optical entry path positioned above the surface region, receives cathodoluminescent light emission arising from the electron beam transferring energy to the surface region. The detector assembly determines spectral characteristics of the cathodoluminescent light emission to characterize the surface region.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 18, 2024
    Applicant: Silanna UV Technologies Pte Ltd
    Inventors: Petar Atanackovic, Dominic Lane
  • Patent number: 11929120
    Abstract: A memory cell comprises a floating gate being disposed between a control gate and a channel, the floating gate being electrically isolated from the control gate and the channel by charge barriers and being configured to enable the selective passage of charge carriers into and out of the floating gate to provide occupancy states of the floating gate. The channel is arranged to provide a minimum threshold voltage to be applied between a control gate and the substrate for introducing charge carriers into the channel from the substrate to make the channel conductive, the minimum threshold voltage being dependent on the occupancy state of the floating gate, such that a read voltage may be applied between the control gate and the substrate that will provide a conductive channel for a first occupancy state of the floating gate and a non-conductive channel for a second occupancy state of the floating gate.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: March 12, 2024
    Assignee: University of Lancaster
    Inventors: Manus Hayne, Dominic Lane
  • Publication number: 20220230686
    Abstract: A memory cell comprises a floating gate being disposed between a control gate and a channel, the floating gate being electrically isolated from the control gate and the channel by charge barriers and being configured to enable the selective passage of charge carriers into and out of the floating gate to provide occupancy states of the floating gate. The channel is arranged to provide a minimum threshold voltage to be applied between a control gate and the substrate for introducing charge carriers into the channel from the substrate to make the channel conductive, the minimum threshold voltage being dependent on the occupancy state of the floating gate, such that a read voltage may be applied between the control gate and the substrate that will provide a conductive channel for a first occupancy state of the floating gate and a non-conductive channel for a second occupancy state of the floating gate.
    Type: Application
    Filed: May 28, 2020
    Publication date: July 21, 2022
    Inventors: Manus Hayne, Dominic Lane