Abstract: Methods and apparatus are provided for performing circular buffer addressing. Upper boundaries, lower boundaries, circular buffer lengths, addresses, and offsets are set to allow circular buffer access efficiency. An addition/subtraction unit is provided to simplify implementation. Comparators are rearranged and in some instances replaced with combined adder/comparator logic units. The additional logic units and the rearrangement allow efficient implementation of circular buffer addressing, particularly on programmable chips.

Abstract: Methods and apparatus are provided for implementing efficient multiplexers on a programmable chip using a lookup table. A load logic input line associated with a lookup table having limited input lines is used to augment the number of input lines that can be handled by a particular lookup table. Load logic and a lookup table having four input lines can be used to implement a 3:1 multiplexer having five input lines.

Abstract: Methods and apparatus are provided for implementing efficient multiplexers on a programmable chip using a lookup table (LUT). A load logic input line associated with a LUT having limited input lines is used to augment the number of input lines that can be handled by a particular LUT. A reset logic input line associated with a LUT is further used to augment the number of input lines. Load logic, reset logic, and a LUT having four input lines can be used to implement a 4:1 multiplexer having seven input lines including four data and three control lines.

Abstract: Adder units are used to compare two numbers. A first logic unit receives one or more bits from a first number and the bits from a second number less the least significant bit of that second number. A second logic unit receives one or more bits from the second number and the bits from the first number less the least significant bit of that first number. The logic units generate, based on the logic values (bits) input into the logic units, logic values and output those values to an adder unit. Using these values, in addition to a “Carry In” value, the adder unit generates an output. The output is at least partially determinative of whether the second number is greater than the first number. Comparators designed in accordance with the present invention incur less delay (i.e., are faster) and require less inputs into logic look-up tables than prior comparators.

Abstract: A multiplexer is configured on a programmable logic device using a plurality of four-input look-up tables chained together. The required number of look-up tables is about one-half the number of inputs of the multiplexer. For an even number of inputs, the number of look-up tables preferably is exactly one-half the number of inputs, while for an odd number of inputs, the number of look-up tables preferably is one-half the number of inputs, plus one-half. The number of control inputs preferably is one more than the number of look-up tables. Preferably, for any one input being a given logic state, and further selected by the one extra input (beyond the number of look-up tables), any particular output may be asserted.