Patents by Inventor Dominic Thurmer
Dominic Thurmer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11804432Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a metal structure above the first main surface. The metal structure has a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness. A polymer-based insulating material contacts and covers at least the periphery region of the metal structure. A thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section. An average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the metal structure, is less than 60 degrees along the periphery region of the metal structure.Type: GrantFiled: February 11, 2021Date of Patent: October 31, 2023Assignee: Infineon Technologies AGInventors: Markus Zundel, Sergey Ananiev, Andreas Behrendt, Holger Doepke, Uwe Schmalzbauer, Michael Sorger, Dominic Thurmer
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Publication number: 20220254713Abstract: A semiconductor device includes a semiconductor substrate having a first main surface and a metal structure above the first main surface. The metal structure has a periphery region that includes a transition section along which the metal structure transitions from a first thickness to a second thickness less than the first thickness. A polymer-based insulating material contacts and covers at least the periphery region of the metal structure. A thickness of the polymer-based insulating material begins to increase on a first main surface of the metal structure that faces away from the semiconductor substrate and continues to increase in a direction towards the transition section. An average slope of a surface of the polymer-based insulating material which faces away from the semiconductor substrate, as measured with respect to the first main surface of the metal structure, is less than 60 degrees along the periphery region of the metal structure.Type: ApplicationFiled: February 11, 2021Publication date: August 11, 2022Inventors: Markus Zundel, Sergey Ananiev, Andreas Behrendt, Holger Doepke, Uwe Schmalzbauer, Michael Sorger, Dominic Thurmer
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Patent number: 9761689Abstract: The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.Type: GrantFiled: September 12, 2014Date of Patent: September 12, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Dominic Thurmer, Hans-Juergen Thees, Kai Frohberg, Peter Moll, Heike Scholz
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Patent number: 9646838Abstract: A method includes providing a semiconductor structure including at least one first circuit element including a first semiconductor material and at least one second circuit element including a second semiconductor material. A dielectric layer having an intrinsic stress is formed that includes a first portion over the at least one first circuit element and a second portion over the at least one second circuit element. A first annealing process is performed, wherein an intrinsic stress is created at least in the first semiconductor material by stress memorization, and thereafter the first portion of the dielectric layer is removed. A layer of a metal is formed, and a second annealing process is performed, wherein the metal and the first semiconductor material react chemically to form a silicide. The second portion of the dielectric layer substantially prevents a chemical reaction between the second semiconductor material and the metal.Type: GrantFiled: June 2, 2014Date of Patent: May 9, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Dominic Thurmer, Sven Metzger, Joachim Patzer, Markus Lenski
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Patent number: 9368513Abstract: A semiconductor device includes a semiconductor material positioned above a substrate and a gate structure positioned above a surface of the semiconductor material, the gate structure covering a non-planar surface portion of the surface. A sidewall spacer is positioned adjacent to the gate structure and includes first dopants having one of an N-type and a P-type conductivity, wherein the sidewall spacer covers an entire sidewall surface of the gate structure and partially covers the surface of the semiconductor material. Source/drain extension regions that include the first dopants are positioned within the non-planar surface portion and in alignment with the sidewall spacer, wherein a concentration of the first dopants within a portion of the sidewall spacer proximate the non-planar surface portion substantially corresponds to a concentration of the first dopants within the source/drain extension regions proximate the non-planar surface portion.Type: GrantFiled: November 6, 2015Date of Patent: June 14, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Gerd Zschätzsch, Stefan Flachowsky, Dominic Thurmer
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Publication number: 20160079086Abstract: The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.Type: ApplicationFiled: September 12, 2014Publication date: March 17, 2016Inventors: Dominic Thurmer, Hans-Juergen Thees, Kai Frohberg, Peter Moll, Heike Scholz
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Patent number: 9209274Abstract: The present disclosure provides in various aspects methods of forming a semiconductor device, methods for forming a semiconductor device structure, a semiconductor device and a semiconductor device structure. In some illustrative embodiments herein, a gate structure is formed over a non-planar surface portion of a semiconductor material provided on a surface of a substrate. A doped spacer-forming material is formed over the gate structure and the semiconductor material and dopants incorporated in the doped spacer-forming material are diffused into the semiconductor material close to a surface of the semiconductor material so as to form source/drain extension regions. The fabricated semiconductor devices may be multi-gate devices and, for example, comprise finFETs and/or wireFETs.Type: GrantFiled: July 19, 2013Date of Patent: December 8, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Gerd Zschaetzsch, Stefan Flachowsky, Dominic Thurmer
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Patent number: 9184260Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. First sidewall spacers are formed adjacent to sidewalls of the gate electrode structure, and the first sidewall spacers include a nitride. An oxide etchant is applied to a surface of the semiconductor substrate after forming the first sidewall spacers. A second spacer material that includes a nitride is deposited over the semiconductor substrate and the first sidewall spacers to form a second spacer layer after applying the oxide etchant to the surface of the semiconductor substrate. The second spacer layer is etched with a second spacer etchant to form second sidewall spacers.Type: GrantFiled: November 14, 2013Date of Patent: November 10, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Joanna Wasyluk, Dominic Thurmer, Ardechir Pakfar, Markus Lenski
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Patent number: 9177874Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an optical planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.Type: GrantFiled: August 28, 2013Date of Patent: November 3, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Joachim Patzer, Ardechir Pakfar, Dominic Thurmer, Chih-Chun Wang, Remi Riviere, Robert Melzer, Bastian Haussdoerfer, Martin Weisheit
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Patent number: 9034746Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.Type: GrantFiled: October 27, 2014Date of Patent: May 19, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Joachim Patzer, Ardechir Pakfar, Clemens Fitz, Dominic Thurmer
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Publication number: 20150132914Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. First sidewall spacers are formed adjacent to sidewalls of the gate electrode structure, and the first sidewall spacers include a nitride. An oxide etchant is applied to a surface of the semiconductor substrate after forming the first sidewall spacers. A second spacer material that includes a nitride is deposited over the semiconductor substrate and the first sidewall spacers to form a second spacer layer after applying the oxide etchant to the surface of the semiconductor substrate. The second spacer layer is etched with a second spacer etchant to form second sidewall spacers.Type: ApplicationFiled: November 14, 2013Publication date: May 14, 2015Applicant: GLOBALFOUNDRIES, Inc.Inventors: Joanna Wasyluk, Dominic Thurmer, Ardechir Pakfar, Markus Lenski
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Publication number: 20150064812Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an organic planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.Type: ApplicationFiled: August 28, 2013Publication date: March 5, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Joachim Patzer, Ardechir Pakfar, Dominic Thurmer, Chih-Chun Wang, Remi Riviere, Robert Melzer, Bastian Haussdoerfer, Martin Weisheit
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Publication number: 20150044861Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.Type: ApplicationFiled: October 27, 2014Publication date: February 12, 2015Inventors: Joachim Patzer, Ardechir Pakfar, Clemens Fitz, Dominic Thurmer
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Publication number: 20150031179Abstract: A method includes providing a semiconductor structure including at least one first circuit element including a first semiconductor material and at least one second circuit element including a second semiconductor material. A dielectric layer having an intrinsic stress is formed that includes a first portion over the at least one first circuit element and a second portion over the at least one second circuit element. A first annealing process is performed, wherein an intrinsic stress is created at least in the first semiconductor material by stress memorization, and thereafter the first portion of the dielectric layer is removed. A layer of a metal is formed, and a second annealing process is performed, wherein the metal and the first semiconductor material react chemically to form a silicide. The second portion of the dielectric layer substantially prevents a chemical reaction between the second semiconductor material and the metal.Type: ApplicationFiled: June 2, 2014Publication date: January 29, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Dominic Thurmer, Sven Metzger, Joachim Patzer, Markus Lenski
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Publication number: 20150021712Abstract: The present disclosure provides in various aspects methods of forming a semiconductor device, methods for forming a semiconductor device structure, a semiconductor device and a semiconductor device structure. In some illustrative embodiments herein, a gate structure is formed over a non-planar surface portion of a semiconductor material provided on a surface of a substrate. A doped spacer-forming material is formed over the gate structure and the semiconductor material and dopants incorporated in the doped spacer-forming material are diffused into the semiconductor material close to a surface of the semiconductor material so as to form source/drain extension regions. The fabricated semiconductor devices may be multi-gate devices and, for example, comprise finFETs and/or wireFETs.Type: ApplicationFiled: July 19, 2013Publication date: January 22, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Gerd Zschaetzsch, Stefan Flachowsky, Dominic Thurmer
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Patent number: 8906794Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.Type: GrantFiled: August 1, 2013Date of Patent: December 9, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Joachim Patzer, Ardechir Pakfar, Clemens Fitz, Dominic Thurmer
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Publication number: 20140353733Abstract: Semiconductor device structures at advanced technologies are provided, wherein a reliable encapsulation of a gate dielectric is already formed during very early stages of fabrication. In illustrative embodiments, a gate stack is formed over a surface of a semiconductor substrate and a sidewall spacer is formed adjacent to the gate stack for covering sidewall surfaces of the gate stack. An additional thin layer is formed over the sidewall spacer, the gate stack and the surface of the semiconductor substrate, and thereafter source/drain extension regions are implanted through the additional thin layer into the substrate in alignment with the sidewall spacer.Type: ApplicationFiled: June 4, 2013Publication date: December 4, 2014Inventors: Gabriela Dilliway, Dina H. Triyoso, Ardechir Pakfar, Markus Lenski, Dominic Thurmer
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Patent number: 7598109Abstract: Thin films, which are deposited on a sacrificial film on a substrate, are released and bonded back on a substrate surface. This technology provides open and closed 2D confined micro-/nano-channels and channel networks on a substrate surface. The geometry, size and complexity of the channels and channel networks can be modified by the film and substrate properties as well as the treatment techniques of the sacrificial layer etching. A method to fabricate such structures with position- and pattern-controllability is provided.Type: GrantFiled: January 29, 2007Date of Patent: October 6, 2009Assignee: Max-Plank-Gesellschaft zur Forderung der Wissenschaften E.V.Inventors: Oliver G. Schmidt, Yongfeng Mei, Dominic Thurmer, Francesca Cavallo
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Publication number: 20070178655Abstract: Thin films, which are deposited on a sacrificial film on a substrate, are released and bonded back on a substrate surface. This technology provides open and closed 2D confined micro-/nano-channels and channel networks on a substrate surface. The geometry, size and complexity of the channels and channel networks can be modified by the film and substrate properties as well as the treatment techniques of the sacrificial layer etching. A method to fabricate such structures with position- and pattern-controllability is provided.Type: ApplicationFiled: January 29, 2007Publication date: August 2, 2007Inventors: Oliver G. Schmidt, Yongfeng Mei, Dominic Thurmer, Francesca Cavallo